Abstract: A buried insulating film is formed in an LDD region between a source region and a drain region, and a non-doped silicon film is formed in the SOI layer above the buried insulating film. The SOI layer lying under the buried insulating film has a body concentration of 1018 cm?3.

Abstract: The invention includes three-dimensional TFT based stacked CMOS inverters. Particular inverters can have a PFET device stacked over an NFET device. The PFET device can be a semiconductor-on-insulator thin film transistor construction, and can be formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The thin film of semiconductor material can comprise both silicon and germanium. Further, the thin film can contain two different layers. A first of the two layers can have silicon and germanium present in a relaxed crystalline lattice, and a second of the two layers can be a strained crystalline lattice of either silicon alone, or silicon in combination with germanium. The invention also includes computer systems utilizing such CMOS inverters.

Abstract: An electrically-programmable memory cell programmed by means of injection of channel hot electrons into a charge-storage element capacitively coupled to a memory cell channel for modulating a conductivity thereof depending on a stored amount of charge. A first and a second spaced-apart electrode regions are formed in a semiconductor layer and define a channel region there between; at least one of the first and second electrode regions acts as a programming electrode of the memory cell. A control electrode is capacitively coupled to the charge-storage element. The charge-storage element is placed over the channel to substantially extend from the first to the second electrode regions, and is separated from the channel region by a dielectric layer. The dielectric layer has a reduced thickness in a portion thereof near the at least one programming electrode.

Abstract: A semiconductor-on-insulator chip is provided which includes a substrate that is formed of an electrically insulating material; a semiconducting layer overlying the substrate; a first region in the semiconducting layer that has a first thickness, the first region includes silicon regions defined by a shallow trench isolation; and a second region in the semiconducting layer that has a second thickness, the second region includes active regions defined by mesa isolation.

Abstract: A semiconductor stacking structure and method of producing the same has a flexible substrate. A plurality of apertures is formed on the flexible substrate. The plurality of apertures may be formed in groups for coupling semiconductor devices to the flexible substrate. A plurality of traces is formed on the flexible substrate for coupling the plurality of apertures together. A first semiconductor device is coupled to a first side of the flexible substrate. A first adhesive layer is placed on a first side of the flexible substrate for coupling the first semiconductor device to the first side of the flexible substrate. A plurality of contacts is coupled to a second side of the flexible substrate. The contacts and the first adhesive layer liquefy and flow into designated apertures when heated to couple the contacts to the first semiconductor device.

Abstract: A structure includes a diffusion barrier layer pattern, a conductive layer pattern, an adhesion layer pattern, and a tantalum nitride layer pattern that are sequentially stacked over a semiconductor substrate. According to the method of forming the structure, a tantalum nitride layer is formed by using a PVD, CVD, or ALD process and patterned to form a tantalum nitride layer pattern. The structure and the method prevents process failures such as ring defects, simplifies associated processes, and allows relatively easy exposure of only an anti-refractive layer when forming a via hole in the structure.

Abstract: The present invention provides a solid-state imaging device comprising: a transparent substrate transmitting light therethrough; a first chip including a solid-state imaging element having a light receiving portion; a first resin providing airtight sealing between the first chip and the transparent substrate; a second chip opposite to the transparent substrate with respect to the first chip; and second resin die bonding the second chip to the first chip, wherein the first resin and the second resin are made of the same material.

Abstract: The present disclosure relates to a data storage device, comprising a plurality of electron emitters adapted to emit electron beams, the electron emitters each having a planar emission surface, and a storage medium in proximity to the electron emitter, the storage medium having a plurality of storage areas that are capable of at least two distinct states that represent data, the state of the storage areas being changeable in response to bombardment by electron beams emitted by the electron emitters.

Abstract: An organic EL device which includes a first electrode, a hole transport layer, a light-emitting layer, and the second electrode, wherein the light-emitting layer includes a mixed light-emitting film of a host substance, which is capable of transferring an energy to another light-emitting polymer by absorbing the energy, and a phosphorescent dopant which is capable of emitting light using a triplet state after absorbing the energy received. Accordingly, the light-emitting layer can be patterned, and a color purity and light-emitting characteristics of a full color organic polymer EL device, produced through a laser induced termal imaging operating, can be improved.

Abstract: A semiconductor memory device having a hierarchical I/O line structure is provided. The semiconductor memory array includes a memory cell array which is divided into a plurality of sub-arrays by sub-word line driver areas and bit line sense amplifier areas; local input/output (I/O) lines which are arranged in the bit line sense amplifier areas; and global I/O lines which are arranged in the sub-word line driver areas, wherein at least one end of each of the local I/O lines is formed in a bit line sense amplifier area. The semiconductor memory device may also have a dummy bit line sense amplifier area capable of dividing local I/O lines in a bit line sense amplifier area, and can reduce the number of sub-word line driver areas such that the chip size can be reduced.

Abstract: A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

Abstract: A padless high density circuit board and manufacturing method thereof. The method includes providing a circuit board substrate, forming external wiring, having a plurality of external terminals with a width as large as or less than the external wiring on the circuit board substrate, forming a solder mask over the circuit board substrate and the external wiring with a plurality of solder mask openings exposing the external terminals, with diameters at least as large as the widths of the external terminals exposed thereby, and forming a plurality of conductive bumps on the external terminals exposed by the solder mask openings for connection with an external device in a subsequent assembly process.

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits.

Abstract: A light shield film is provided adjacent to an anode of an EL element that consists of the anode, an EL layer, and a cathode. The anode and the cathode are transparent or semitransparent to visible light and hence transmit EL light. With this structure, ambient light is absorbed by the light shield film and does not reach an observer. This prevents an external view from appearing on the observation surface.

Abstract: A recess is formed in a substrate, a pair of electrodes is provided on the surface of the substrate including a surface of the recess. An LED is provided on the bottom of the recess. A transparent sealing plate is provided for closing the recess.

Abstract: An electronic circuit assembly having a fiducial on a lower layer substrate. The fiducial is viewed through a through hole that is aligned with the fiducial and extends through an upper layer substrate that is adjacent the lower layer substrate. The fiducial and the through hole provide a high contrast between the fiducial and the surrounding substrate permitting viewing and recognition of substrate orientation by a computer vision system.

Abstract: A nitride based semiconductor photo-luminescent device has an active layer having a quantum well structure. The active layer has both a high dislocation density region and a low dislocation density region that is lower in dislocation density than the high dislocation density region, wherein the low dislocation density region includes a current injection region into which a current is injected, and the active layer is less than 1×1018 cm?3 in impurity concentration.

Abstract: A semiconductor structure includes a monocrystalline silicon substrate, an amorphous oxide material overlying the monocrystalline silicon substrate, a monocrystalline perovskite oxide material overlying the amorphous oxide material, and a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material. A composite transistor includes a first transistor having first active regions formed in the monocrystalline silicon substrate, a second transistor having second active regions formed in the monocrystalline compound semiconductor material, and a mode control terminal for controlling the first transistor and the second transistor.

Abstract: A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 ?m2 to about 10 ?m2. The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.

Abstract: A microelectronic assembly includes composite conductive elements, each incorporating a core and a coating of a low-melting conductive material. The composite conductive elements interconnect microelectronic elements. At the normal operating temperature of the assembly, the low-melting conductive material melts, allowing the cores and microelectronic elements to move relative to one another and relieve thermally-induced stress.