Abstract: A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a flange in contact with the substrate, allowing a plurality of clip members to clamp the flange of the heat sink and the substrate. Each of the clip members has a recess portion for receiving the flange of the heat sink and the substrate to thereby firmly position the heat sink on the substrate. The clip members are engaged with edges of the heat sink and the substrate, thereby not affecting trace routability on the substrate. Moreover, the heat sink is mounted on the substrate and would not be dislocated.

Abstract: A method for fabricating a radiation-emitting semiconductor chip having a thin-film element based on III-V nitride semiconductor material includes the steps of depositing a layer sequence of a thin-film element on an epitaxy substrate. The thin-film element is joined to a carrier, and the epitaxy substrate is removed from the thin-film element. The epitaxy substrate has a substrate body made from PolySiC or PolyGaN or from SiC, GaN or sapphire, which is joined to a grown-on layer by a bonding layer, and on which the layer sequence of the thin-film element is deposited by epitaxy.

Abstract: An integrated circuit package comprises a cavity for housing an integrated circuit (IC) and an antenna provided as part of the package that is located substantially outside the cavity. The antenna may be located on the floor of the IC package that lies in the region outside of the IC cavity. Alternatively, the antenna may be located on the upper or lower surface of the lid sealing the IC package. The antenna may be placed in the floor or on a surface of the IC lid by forming depressions in the floor or lid surface and depositing conductive material in the depressions. The conductive material deposition may be by sputtering, evaporation, or other known physical or chemical deposition method. Antennas formed in the upper surface of an IC lid may be coupled to a pin of the IC package so that the antenna may be electrically coupled to a transceiver component on the IC within the package.

Abstract: An electronic apparatus, including a plate-like member, enclosing a heat-accumulating material of latent heat type within an inside thereof; a semiconductor element, being connected with the member, thermally; and a housing covering the semiconductor element and the member. A surface of the member, in contact with the semiconductor element, is provided with recess-portions in plural numbers thereof, each being recessed in a direction of the heat-accumulating material of latent heat type, so as to enclose the heat-accumulating material of latent heat type into the recess portions. The plate-like member and the housing are connected with each other, thermally, thereby providing a cooling device, being able to cool the electronic circuit component(s) building up the electronic apparatus, as well as being superior in operability.

Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bump formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film formed in at least a peripheral portion of the bump to cover an interface of the bump and the intermediate layer which is exposed to a side surface of the bump.

Abstract: In a semiconductor pressure sensor device comprising a housing (1) having a cavity (3), a semiconductor sensor chip (2) mounted within the cavity, leads (4) for conveying pressure detection signals, and bonding wires (6) electrically connecting the sensor chip and the leads, a sensitive portion (2a) of sensor chip (2), leads (4) and bonding wires (6) are covered with an electrically insulating fluorochemical gel material which has a penetration of 30-60 according to JIS K2220, a Tg of up to ?45° C., and a degree of saturation swelling in gasoline at 23° C. of up to 7% by weight. The sensor device is improved in operation reliability and durability life.

Abstract: An inter-level insulator structure is provided having an effective insulator dielectric constant approaching 1. An embodiment of the inter-level insulator comprises a first metal layer comprising a first plurality of metal lines; a second metal layer comprising a second plurality of metal lines, and at least one via connected to the first metal layer; and an air gap interposed between the first metal layer and the second metal layer. In one embodiment, the air gap is also present between metal lines on either metal layer, such that air gaps act as intra-level as well as inter-level insulators. A method is also provided to deposit and pattern a sacrificial polymer, and form metal layers. The sacrificial polymer is capable of being decomposed to become air gaps during annealing.

Abstract: A light emitting diode package structure includes an insulating carrier base formed with a recess or a through hole. The recess or the through hole has a depth enough for completely accommodating a light emitting diode. The recess or the through hole may have two stepwise portions for providing two intermediate mesa planes. Two planar metal layers are separately formed on the two intermediate mesa planes and, respectively, connected to two metal pads which are arranged outside of the recess or the through hole. Two wiring lines connect two electrodes of the light emitting diode with the two planar metal layers, respectively. A resin fills the recess or the through hole for sealing all of the light emitting diode and the two wiring lines.

Abstract: In a semiconductor device circuit formation surfaces of each of a plurality of semiconductor chips can be easily located at even level when the semiconductor chips are arranged side by side so that a process of forming rearrangement wiring is simplified. The semiconductor chips are mounted on a substrate via an adhesive layer in a two-dimensional arrangement. A resin layer is formed on the substrate and located around the semiconductor elements. The resin layer has the same thickness as a thickness of the semiconductor elements. An organic insulating layer is formed over a surface of the resin layer and circuit formation surfaces of the semiconductor elements. A rearrangement wiring layer is formed on the organic insulating layer and electrodes of the semiconductor chips. External connection terminals are electrically connected to the circuit formation surfaces of the semiconductor elements through wiring in the rearrangement wiring layer.

Abstract: In silicon carbide semiconductor device and manufacturing method therefor, a metal electrode which is another than a gate electrode and which is contacted with a singlecrystalline silicon carbide substrate is treated with a predetermined heat process at a temperature which is lower than a thermal oxidization temperature by which a gate insulating film is formed and is sufficient to carry out a contact annealing between the singlecrystalline silicon carbide substrate and a metal after a whole surrounding of the gate insulating film is enclosed with the singlecrystalline silicon carbide substrate, a field insulating film, and the gate electrode. The present invention is applicable to a MOS capacitor, an n channel planar power MOSFET, and an n channel planar power IGBT.

Abstract: A method of reducing dopant losses is provided. The method includes providing a transistor structure having a first region, implanting a dopant into the first region, depositing a control layer adjacent the first region, and performing a first annealing process on the transistor structure. The control layer is operable to prevent at least a portion of the dopant in the first region from diffusing out of the first region toward the control layer during the first annealing process.

Abstract: A dummy structure pattern for fabricating a substantially planar surface within an inactive region of a semiconductor topography is provided. In particular, a semiconductor topography is provided which includes an inactive region comprising a sacrificial annular dummy structure configured to surround an area larger than a square of a minimum critical dimension of a device arranged within an active region of the semiconductor topography. In a preferred embodiment, the area is exclusively designated for a formation of an isolation structure within the semiconductor substrate of the semiconductor topography. As such, a semiconductor topography is provided which includes a separate isolation structure arranged within a spacing of a contiguous isolation structure, which is arranged in a grid pattern within a portion of a semiconductor substrate. Moreover, a semiconductor device is provided which includes an inactive region with a plurality of similarly sized and uniformly arranged annular diffusion regions.

Abstract: A semiconductor structure includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness.

Abstract: The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.

Abstract: This invention describes new LEDs having light extraction structures on or within the LED to increase its efficiency. The new light extraction structures provide surfaces for reflecting, refracting or scattering light into directions that are more favorable for the light to escape into the package. The structures can be arrays of light extraction elements or disperser layers. The light extraction elements can have many different shapes and are placed in many locations to increase the efficiency of the LED over conventional LEDs. The disperser layers provide scattering centers for light and can be placed in many locations as well. The new LEDs with arrays of light extraction elements are fabricated with standard processing techniques making them highly manufacturable at costs similar to standard LEDs. The new LEDs with disperser layers are manufactured using new methods and are also highly manufacturable.

Abstract: A self-organized nanometer interface structure is disclosed. During the reactive sputtering process, the chemical dynamics difference among reactants induces self-organization to form a special nanometer interface structure. The nanometer interface structure naturally form an interface potential difference so that it has a rectifying effect in a particular range of potential variation range. Therefore, it functions like a diode. Such a self-organized nanometer interface structure can be used in the manufacturing of diodes, transistors, light-emitting devices, and sonic devices. The invention has the advantages of a wide variety of material selections, highly compatible processes, easy operations, and low-cost fabrications.

Abstract: A method for enhancing the on-current carrying capability of a MOSFET device is disclosed. In an explanary embodiment, the method includes recessing fill material formed within a shallow trench isolation (STI) adjacent the MOSFET so as to expose a desired depth of a sidewall of the STI, thereby increasing the effective size of a parasitic corner device of the MOSFET. The threshold voltage of the parasitic corner device is then adjusted so as to substantially equivalent to the threshold voltage of the MOSFET device.

Abstract: Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias.

Abstract: An organic light emitting diode (OLED) device comprises a substrate, an anode layer, a luminescence layer, a hole blocking layer and a cathode layer. The anode layer is disposed on the substrate; the luminescence layer is disposed on the anode layer; the hole blocking layer is disposed on the luminescence layer; the cathode layer is disposed on the hole blocking layer. In addition the luminescence layer comprises a hole transporting material and a phosphorescent material, wherein the weight percentage of the bole transporting material and the phosphorescent material is between 40%˜60%.

Abstract: A semiconductor light-emitting device includes an active layer having a single quantum well structure. The single quantum well structure enables a high-speed response such that the rise and fall time is 2.1 nsec. Further, the single quantum well active layer is doped with Zn at a concentration of 8×1017 cm−3. Thereby, the half-value width of the light-emitting spectrum is 25 nm or more, which is wider than in the case of no doping. Thus, temperature dependence of an optical output is reduced.