Abstract: Process of manufacturing a semiconductor device comprising a step of forming recessed zones in a semiconductor layer of a first conductivity type, a step of oxidation for forming a gate oxide layer at the sidewalls of the recessed zones, a step of forming a polysilicon gate electrode inside the recessed zones, a step of forming body regions of a second conductivity type in the semiconductor layer between the recessed zones, and a step of forming source regions of the first conductivity type in the body regions. The step of forming recessed zones comprises a step of local oxidation of the surface of the semiconductor layer wherein the recessed zones will be formed, with an oxide growth at the semiconductor layer's cost in order to obtain thick oxide regions penetrating in the semiconductor layer, and a step of etching wherein the oxide of the thick oxide regions is removed.

Abstract: A selenidation reaction for bonding one or more active substrates to a base substrate is disclosed. A bonded-substrate is fabricated by forming a first multi-stacked layer of selenium and indium on a bonding surface of an active substrate and forming a second multi-stacked layer of selenium and indium on a mounting surface of a base substrate. The first and second multi-stacked layers are placed into contact with each other with substantially no pressure. Then the active substrate and the base substrate are bonded to each other by annealing them in an inert ambient to form an indium-selenium compound bond layer that adhesively bonds the substrates to each other. The annealing can occur at a lower temperature than prior wafer-bonding processes and the first and second multi-stacked layers can be deposited over a wide range of relatively low temperatures including room temperature.

Abstract: A method of forming a vertical transistor in an integrated circuit using copolymer lithography includes providing a dielectric layer over a semi-conductor substrate and depositing a layer of copolymer over the dielectric layer. The copolymer has a first polymer type and a second polymer type. The method further includes removing a portion of the first polymer type from the copolymer layer to form a void in the copolymer layer and removing a portion of the dielectric layer underlying the void to form an aperture in the dielectric layer. The method further includes providing a semiconductor material in the aperture.

Abstract: A method of fabricating a vertical transistor of a memory cell is disclosed. Accordinng to this method, a semiconductor substrate is first provided. A pad layer is formed on the surface of the substrate. A deep trench is formed in the substrate. In the deep trench, a trench capacitor is formed, a collar oxide layer is then formed on the sidewalls above the trench capacitor. A first conductive layer is formed above the trench capacitor. A second conductive layer is deposited to form a buried strap and an opening. A first insulating layer and a second masking layer are formed and fill the opening. The pad layer, the substrate, the second masking layer, the first insulating layer, the collar oxide layer and the first conductive layer are patterned. A second insulating layer is deposited and forms a Shallow Trench Isolation. A portion of the second masking layer is removed. The pad layer is removed to expose the substrate. A well is formed in the exposed substrate after forming a third insulating layer.

Abstract: A method for forming a via through a dielectric layer. There is first provided a substrate. There is then formed over the substrate a patterned conductor layer. There is then formed covering the patterned conductor layer a dielectric layer. There is then formed through the dielectric layer a via to access the patterned conductor layer, where the via is incompletely landed upon the patterned conductor layer. There is then purged the via while employing a vacuum purging method to form a purged via. There is then passivated the purged via and passivated the patterned conductor layer exposed within the purged via while employing a plasma passivation method to form a plasma passivated purged via and a plasma passivated patterned conductor layer. Finally, there is then formed into the plasma passivated purged via a conductor stud layer.

Abstract: A method for manufacturing a trench capacitor uses a low-pressure gas phase doping for forming a buried plate as a capacitor plate. The use of the low-pressure gas phase doping reduces process costs and improves capacitor properties.

Abstract: A silicon-on-insulator substrate and its method of formation are disclosed. In another embodiment, a method for forming a high-k gate dielectric is disclosed. The silicon-on-insulator substrate is prepared by forming a lattice matched dielectric layer (20) over a semiconductor substrate (10). A thermodynamically stable dielectric layer (22) is then formed over the lattice matched dielectric layer (20). A semiconductor layer (30) is then formed over the thermodynamically stable dielectric layer (22). Formation of the high-k gate dielectric includes the processing steps used to form the silicon-on-insulator substrate and additionally includes bonding a second semiconductor substrate (50) to the semiconductor layer (30). The first semiconductor substrate (10) is then removed to expose the lattice matched dielectric layer (20). This results in a silicon substrate that has a layer of high-k dielectric material that can be used as the gate dielectric for integrated circuits formed on the substrate.

Abstract: A method of manufacturing a HEMT IC using a citric acid etchant. In order that gates of different sizes may be formed with a single etching step, a citric acid etchant is used which includes potassium citrate, citric acid and hydrogen peroxide. The wafer is first spin coated with a photoresist which is then patterned by optical lithography. The wafer is dipped in the etchant to etch the exposed semiconductor material. Metal electrodes are evaporated onto the wafer and the remaining photoresist is removed with solvent.

Abstract: A new method of forming MOS transistors with self-aligned silicide has been achieved. A gate oxide layer is formed overlying a semiconductor substrate. A polysilicon layer is deposited. The polysilicon layer and the gate oxide layer are patterned to form gates. Ions are implanted to form lightly doped drain regions. A dielectric layer is deposited. The dielectric layer is polished down to expose the top surface of the gates. The dielectric layer is then anisotropically etched down to form dielectric sidewall spacers. The dielectric sidewall spacers cover a portion of the vertical sidewalls of the gates while exposing a portion of the vertical sidewalls of the gates. Ions are implanted to form source and drain regions. A metal layer is deposited. Contact surfaces are formed between the metal layer with: the exposed top surfaces of the gates, the exposed portions of the vertical sidewalls of the gates, and the exposed source and drain regions.

Abstract: An aluminum layer formed over an integrated circuit structure is patterned to form a plurality of aluminum metal lines. The patterned aluminum metal lines are then anodized in an acid anodizing bath to form anodized aluminum oxide on the exposed sidewall surfaces of the patterned aluminum. The anodization may be carried out until the anodized aluminum films on horizontally adjacent aluminum metal lines contact one another, or may be stopped prior to this point, leaving a gap between the anodized aluminum oxide films on adjacent aluminum metal lines. This gap may then be either filled with other low k dielectric material or by standard (non-low k) dielectric material. A capping layer of non-porous dielectric material is then formed over the porous anodized aluminum oxide.

Abstract: The method for manufacturing a Semiconductor Memory according to the present invention comprises a step for forming a gate insulator film on the surface of a semiconductor substrate; a step for forming a mask layer having a through-hole provided in the position where a tunnel window is to be formed, on top o said gate insulator film; a step for forming an impurity region in the vicinity of the surface of said semiconductor substrate by introducing an impurity using the mask layer; and a step for forming a tunnel insulator film on the surface of the semiconductor substrate, using a mask layer. In the present invention, the position in which the source is formed and the position in which the tunnel window is formed are determined by means of the position of the same through-hole. Therefore, the manufacturing error in the distance between the tunnel window and the source can be nullified.

Abstract: The present invention relates to nanoporous dielectric films and to a process for their manufacture. Such films are useful in the production of integrated circuits. A precursor of an alkoxysilane, and low and high volatility solvents are mixed at a pH of about 2-5, raised to a pH of about 8 or above with a low volatility base and deposited on a semiconductor substrate. After exposure to atmospheric moisture, a nanoporous dielectric film is produced on the substrate.

Abstract: The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped (139) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure (144) down to a depth lower than the depth of the surrounding field oxide (120), and that the semiconductor structure (144) is then heat treated.

Abstract: A method of forming bonds between similar and dissimilar material surfaces particularly the surfaces of silicon wafers having various devices disposes thereon, wherein such bonds can be formed at room temperature and do not require the application of high pressures or voltages. The bonding material is polydimethylsiloxane, which is transparent and bio-compatible.

Abstract: In accordance with one embodiment of the invention, a diffusion barrier layer is formed in a copper interconnect structure by first forming a layer of intermetal dielectric material on an underlying layer of conductive material. A pattern of dual damascene structures is then formed in the interconnect dielectric layer. An adhesion layer is then formed on exposed sidewalls of the damascene structure and on the upper surface of the intermetal dielectric material. The adhesion-layer-lined dual damascene structures are then filled with a conductive material that includes copper. The copper-including conductive material is then planarized to the upper surface of the intermetal dielectric material. Intermetal dielectric material is then removed to expose the conductive material. A diffusion barrier material is then deposited on exposed surfaces of the conductive material.

Abstract: In the manufacture of a trench-gate semiconductor device, for example a MOSFET or an IGBT, a starting semiconductor body (10) has two top layers (13, 15) provided for forming the source and body regions. Gate material (11′) is provided in a trench (20) with a trench etchant mask (51, FIG. 2) still present so that the gate material (11′) forms a protruding step (30) from the adjacent surface (10a) of the semiconductor body, and a side wall spacer (32) is then formed in the step (30) to replace the mask (51). The source region (13) is formed self-aligned with the protruding trench-gate structure with a lateral extent determined by the spacer (32, FIG. 5), and the gate (11) is then provided with an insulating overlayer (18, FIG. 6).

Abstract: A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

Abstract: A method for manufacturing integrated circuits (“IC”) on wafers to manage crack damage in the ICs such that crack propagation into the IC active array is reduced or eliminated. The method provides for a defined separation or divide of the IC gate conductor from the IC crack stop or IC edge. The method is especially useful in managing crack damage induced through the delamination of one or more of the gate conductor surface interfaces as a result of the IC wafer dicing process. Circuits or chips manufactured according to the methods disclosed are also taught.

Abstract: Performance of the high resistance resistor, which is polysilicon, is improved by treating the surface of the polysilicon layer in mixed signal integrated circuits for ADSL (Asymmetric Digital Subscriber Line) broadband service application. This treated surface of the polysilicon layer will prevent ions in the resistor from out-diffusion when performing an annealing step after forming the resistor.

Abstract: One aspect of the present invention relates to a method of forming a low k material layer on a semiconductor substrate, involving the steps of depositing a mixture containing a low k material and a casting solvent on the semiconductor substrate; optionally contacting the mixture with a transition solvent whereby the casting solvent is removed from the mixture to form a second mixture containing the low k material and the transition solvent; contacting the second mixture with a supercritical fluid whereby the transition solvent is removed from the second mixture; and permitting the supercritical fluid to evaporate thereby forming the low k material layer.