Abstract: Disclosed is a semiconductor device comprising a transistor structure including an epitaxial silicon layer formed on a main surface of an n-type semiconductor substrate, source-drain diffusion layers formed on at least the epitaxial silicon layer, a channel region formed between the source and drain regions, and a gate electrode formed on the channel region with a gate insulating film interposed therebetween, an element isolation region being sandwiched between adjacent transistor structures, wherein a punch-through stopper layer formed in a lower portion of the channel region has an impurity concentration higher than that of the channel region, and the source-drain diffusion layers do not extend to overlap with edge portion of insulating films for the element isolation.

Abstract: The present invention provides a method of forming a gate structure of a floating gate MOS field effect transistor.

Abstract: A method for manufacturing a polysilicon layer includes providing a substrate, forming an amorphous silicon layer on an entire surface of the substrate, defining an active area on the amorphous silicon layer, doping the amorphous silicon layer with a semiconductor material, depositing a metal layer on the amorphous silicon layer; and applying a voltage to the amorphous silicon layer to form a polysilicon layer using a joule heat that is generated from the applied voltage.

Abstract: A method for cladding two or three sides of a top conductor for a magnetic memory device in ferromagnetic material includes forming a trench with side walls in a coating layer above the memory device. A first ferromagnetic material is deposited along the side walls of the trench. Any ferromagnetic material in a bottom of the trench can be removed. A conductor material is deposited in the trench over the memory device. A second ferromagnetic material is deposited over the conductor material in the trench to form a cladding of the ferromagnetic material around three side of the conductor.

Abstract: System and method for determining a respective effective oxide thickness for each of first and second dielectric structures that form a MOS (metal oxide semiconductor) stack. A first plurality of test MOS (metal oxide semiconductor) stacks are formed, and each test MOS stack includes a respective first dielectric structure comprised of a first dielectric material and a respective second dielectric structure comprised of a second dielectric material. A respective deposition time for forming the respective first dielectric structure corresponding to each of the first plurality of test MOS stacks is varied such that a respective first effective oxide thickness of the respective first dielectric structure varies for the first plurality of test MOS stacks. A respective second effective oxide thickness of the respective second dielectric structure is maintained to be substantially same for each of the first plurality of test MOS stacks.

Abstract: Methods of forming thin films include forming a first layer comprising a first element that is chemisorbed to a surface of a substrate, by exposing the surface to a first source gas having molecules therein that comprise the first element and a halogen. A step is then performed to expose the first layer to an activated hydrogen gas so that halogens associated with the first layer become bound to hydrogen provided by the activated hydrogen gas. The first layer may then be converted to a thin film comprising the first element and a second element, by exposing a surface of the first layer to a second source gas having molecules therein that comprise the second element.

Abstract: The invention relates to a method for producing a thin membrane, comprising the following steps: implanting gas species, through one surface of a first substrate (10) and through one surface of a second substrate (20), which in said substrates are able to create microcavities (11, 21) delimiting, for each substrate, a thin layer (13, 23) lying between these microcavities and the implanted surface, the microcavities being able, after their implantation, to cause detachment of the thin layer from its substrate; assembly of the first substrate (10) onto the second substrate (20) such that their implanted surfaces face one another; detaching each thin layer (13, 23) from its substrate (10, 20), the thin layers remaining assembled together to form said thin membrane. The invention also concerns a thin membrane structure obtained with this method.

Abstract: A method of fabricating a gate. A gate dielectric layer is formed, and a lower portion of a floating gate is formed encompassed by a first dielectric layer. Second dielectric layers with different etching rates are formed to cover the upper portion of the floating gate and the first dielectric layer. Using an etching mask, an opening is formed within the second dielectric layer to expose the floating gate and a portion of the second dielectric layers by performing an anisotropic etching process. Using the same etching mask, the second dielectric layers exposed within the opening is further etched by performing an isotropic etching process. Due to the different etching rates, a dielectric layer with an uneven and enlarged surface is formed. A conformal conductive layer is formed on the exposed lower portion of the floating gate and the exposed second dielectric layers as an upper portion of the floating gate.

Abstract: A method of fabricating a trenched flash memory cell is provided. A plurality of shallow trench isolation structures are formed to enclose at least an active area in a silicon substrate. A doped region is formed in the silicon substrate, followed by the deposition of an isolation layer on the silicon substrate. A first photo and etching process (PEP) is performed to form two trenches within the active area. A tunnel oxide layer, a floating gate, and ONO dielectric layer are formed in the trenches, respectively. A doped polysilicon layer is then formed on the silicon substrate to fill the trenches, followed by the removal of a portion of the doped polysilicon layer to form two controlling gates in the active area. Next, a self-alignment common source is formed between the two controlling gates and a plurality of spacers are formed on either side of each controlling gate. Finally, a silicide layer is formed on the surfaces of the controlling gates and the common source.

Abstract: A method for making a layout for an interconnect layer of a semiconductor device to facilitate uniformity of planarization during manufacture of the semiconductor device includes determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout. The method further includes adding dummy fill features to each layout region to obtain a desire density of active interconnect features and dummy fill features to facilitate uniformity of planarization during manufacturing of the semiconductor device. By adding dummy fill features to obtain a desired density of active interconnect features and dummy fill features, dummy fill features are not unnecessarily added, and each layout region has a uniform density.

Abstract: A planarization method includes providing an aluminum-containing surface and positioning it for contact with a fixed abrasive article in the presence of a composition preferably including a surfactant, a complexant, and an oxidant, wherein the solution has a pH of less than about 10.

Abstract: A strained Si CMOS structure is formed by steps which include forming a relaxed SiGe layer on a surface of a substrate; forming isolation regions and well implant regions in said relaxed SiGe layer; and forming a strained Si layer on said relaxed SiGe layer. These processing steps may be used in conjunction with conventional gate processing steps in forming a strained MOSFET structure.

Abstract: A porous layer is formed on an Si substrate using an anodizing apparatus having a conductive partition inserted between a cathode and an anode. First, the cathode and Si substrate are brought into electrical contact through a first electrolyte, and the conductive partition and Si substrate are brought into electrical contact through a second electrolyte. A current is flowed between the cathode and the anode to form a porous layer on the Si substrate. As the first electrolyte, an electrolyte capable of forming a porous structure on the Si substrate is used. As the second electrolyte, an electrolyte substantially incapable of forming a porous structure on the conductive partition is used.

Abstract: A fabrication method for a dual damascene structure is provided. A barrier layer and a copper seed layer are formed on a substrate comprising a dual damascene opening, wherein the barrier layer and the copper seed layer cover the dual damascene opening. A sacrificial layer is then formed on the copper seed layer, filling the dual damascene opening. Using the copper seed layer as an etch stop layer, the sacrificial layer is etch back. The exposed copper seed layer is then removed, followed by completely removing the sacrificial layer. A metal copper layer is formed in the dual damascene opening by plating, filling the opening of the dual damascene opening.

Abstract: A semiconductor device comprises: a support member (20) on which a land (24) is formed; a semiconductor chip (10) having a bump for an electrode (12) that is disposed on the land (24), and to be bonded face-down to a support member (20); and resin (30) which is provided as an adhesive between the semiconductor chip (10) and the support member (20), which is allowed to contract on hardening, and which causes pressure-bonding between the land (24) and the bump (12) by the stress due to this hardening contraction. The stress therein is partially absorbed by elastic deformation of at least the support member (20).

Abstract: A method of removing silicon carbide. A silicon wafer is used as a dummy wafer for inspecting the properties of a silicon carbide thin film which is to be formed thereover. A silicon nitride layer with a thickness larger than about 1000 angstroms is formed on the dummy wafer as a base layer of the silicon carbid thin film. The silicon carbide thin film is then formed on the base layer. The property inspection of the silicon carbide thin film is performed. After the properties inspection, the silicon carbide is stripped using a high density hydrogen plasma. After the step of high density hydrogen plasma, if the remaining silicon nitride layer is thicker than about 500 angstroms, the remaining silicon nitride layer can be used as the base layer again for forming and inspecting the properties of the silicon carbide thin film.

Abstract: A barrier to prevent reactant gases from reaching the surfaces of a susceptor support for a substrate upon which polysilicon films are to be deposited provides improved uniformity of the depositing film across the substrate, and prevents substrate-to-substrate variations during sequential depositions. A suitable barrier includes a preheat ring extension that mates with an extension of the susceptor support.

Abstract: A method for forming a semiconductor device includes providing a lead frame which has a die pad and a plurality of leads extending toward the outside of the die pad, mounting a semiconductor chip on the die pad, defining a plurality of inner leads by cutting a predetermined cut portion on each of the leads located around the semiconductor chip, and bonding a wire between the inner leads and the semiconductor chip. Accordingly, an applicable lead frame is provided for several sizes of a semiconductor chip.

Abstract: In an optical semiconductor device fabrication method for simultaneously forming elements having different operation wavelengths on a circular semiconductor substrate, the number of elements for each operation wavelength is made constant efficiently and the operation characteristics of the elements are made highly uniform, by parabolically changing the operation wavelength of the optical semiconductor device from a center portion of the circular semiconductor substrate toward an outer periphery thereof.

Abstract: A method of forming a triple well structure. A first photoresist layer is formed on a substrate having a first conductive type. A first ion implantation process is performed to form a first well, which has the first conductive type but a dopant concentration of the first well is higher than a dopant concentration of the substrate. The first photoresist layer is baked. A second ion implantation process is performed through the baked first photoresist layer to form a first doped region under the first well. The first doped region has a second conductive type. After removing the first photoresist layer, a second photoresist layer is formed on the substrate. A third ion implantation process is performed to form a second doped region in the substrate around the first well and to form a second well in the substrate. The second doped region and the second well have the second conductive type. The second doped region and the first doped region together surround the first well.