Abstract: Organic etch residues are often left within vias formed by etching through resist masks. Since the etch is designed to expose an underlying metal layer and is directional in order to produce vertical via sidewalls, the residue often incorporates metal. The present invention discloses a method of removing such etch residues while passivating exposed metal, including exposing the residue to ammonia. In the disclosed embodiment, ammonia and oxygen are mixed in a plasma step, such that the resist can be burned off at the same time as the residue treatment. The residue can thus be easily rinsed away.

Abstract: A method for manufacturing a semiconductor device includes the steps of preparing a semiconductor chip with a plurality of bonding pads and a plurality of conductive bumps on the bonding pads, preparing a substrate formed with a plurality of bump receiving holes and a plurality of conductive traces having contact portions adjacent to peripheries of the bump receiving holes, laying the substrate over the semiconductor chip such that the conductive bumps respectively extend through the bump receiving holes, and forming a plurality of conductive bodies, each of which encloses and electrically connects a top portion of a respective one of the conductive bumps to the contact portion of a respective one of the conductive traces.

Abstract: We have discovered particular wetting layer or wetting/barrier layer structures which enable depositing of overlying aluminum interconnect layers having <111> texturing sufficient to provide a Rocking Curve FWHM angle &thgr; of about 1° or less. The aluminum interconnect layer exhibiting a Rocking Curve FWHM angle &thgr; of about 1° or less exhibits excellent electromigration properties. In addition when the aluminum layer is subsequently pattern etched, the sidewalls of the etched aluminum pattern exhibit a surprising reduction in pitting compared with pattern etched aluminum layers exhibiting higher Rocking Curve FWHM angles.

Abstract: A method for preventing boron segregation and out diffusion to form PMOS devices is disclosed. The method includes providing a semiconductor substrates and the formation of a gate oxider layer as well as a gate layer on top of the semiconductor substrate. Next, a photoresist layer is formed on a top surface of the gate layer, moreover, a pattern is transferred onto the photoresist layer after being put through an exposure and a development. Furthermore, the gate layer and the oxide layer are then etched using the photoresist layer as a mask, and the photoresist layer is removed afterward. In succession, a thin silicon nitride layer is grown utilizing RTCVD processing. Thereafter, high doped drain regions of boron ion shallow junctions are formed by carrying out ion implantation. A silicon oxide layer is deposited using LPCVD, and forming spacers by etching the silicon oxide layer. Next, a heavy doping of boron ions proceeds, as well as an annealing process.

Abstract: A unique bond-ply structure and associated processes for processing of the bond-ply structure and for joining together circuit layer pairs which makes it possible to create a bond-ply having raised structures of conductive material which compensate for shrinkage during sintering thus creating a stress-free and void-free electrically conductive junction between layer-pairs in an interconnect.

Abstract: The present invention relates to a method of manufacturing a thin film transistor for use in a liquid crystal display apparatus or the like. In the method, impurity ions are implanted into a semiconductor by intermittently generating a plasma which generates impurity ions, for a predetermined period at a predetermined interval. By changing the duty rate at which the plasma is generated, the effective value of a beam current can be controlled over a wide range with excellent accuracy without changing rates of ions. As a result, it is possible to form a channel portion and a lightly doped drain layer of a field effect transistor which contains silicon as a main component, so that a field effect transistor and a liquid crystal display device can be manufactured with high quality and excellent productivity.

Abstract: A method is disclosed for the formation of ferro-electric films using a multi coating process based on a sol-gel technique. In particular a method is disclosed to fabricate high-quality thickness scaled PZT films of an alkoxide-type liquid chemical PZT precursor solution, preferably a Pb(ZrxTi1−x)O3 precursor solution, using a sol-gel technique. At least two coated layers are deposited, but the precise number of coated layers depends on the desired thickness of the ferro-electric film. According to the method of the invention, the electrical characteristics of the film as formed are not dependent on the number of coated layers. There are a number of properties, characteristic for the method of the present invention, and resulting in said excellent electrical characteristics. In fact said method can comprise a multi coating process wherein a reduced number of coated layers is used but where intermediate crystallization steps are performed.

Abstract: A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

Abstract: A problem in the manufacture of semiconductor wafers exists in that reaction product adhering to a quartz member is peeled off and falls on wafers, thus causing particles to contaminate the wafers. In system of introducing electro-magnetic waves from the outside via the quartz member, an inventive high-density plasma etching system for processing wafers by introducing electro-magnetic waves generated by a TCP electrode into a vacuum chamber via a quartz top board and by generating plasma by exciting gas within the chamber comprises a far infrared ray heater disposed above the quartz top board to heat the quartz top board by radiant heat of infrared rays generated from the far infrared ray heater, reducing the product adhering to the quartz member and thus the contaminating particles, thereby improving the yield of the wafers.

Abstract: For example, in a plasma processing system, C4F8 gas and C2H4 gas are introduced as film-forming gases at flow rates of 60 sccm and 30 sccm, respectively, under the conditions of a pressure of 0.2 Pa, a microwave power of 2.7 kW, a radiofrequency power of 1.5 kW, and a wafer temperature of 350° C. At the same time, a plasma gas is also introduced at a flow rate of 150 sccm to form CF film 13 having an F content of, for example, 22% on silicon substrate 11. This CF film 13 has a relative dielectric constant of 2.4.

Abstract: Method and apparatus for the testing of substrates which are provided with a wiring structure, in particular, chips (21), in conjunction with which, by means of a solder-deposit carrier (25) which is provided with a structured, electrically conductive coating (12) with bond pads (17) for the arranging of solder deposits (28) and their transfer to correspondingly arranged bond pads (22) of a substrate (21), an electrical check of the wiring structure of the substrate (21) takes place during the transfer of the solder deposits (28).

Abstract: A method for manufacturing a thin film AMA is disclosed. The second sacrificial layer is formed by using amorphous silicon, poly silicon or a material having fluidity and the first sacrificial layer is formed by using amorphous silicon or poly silicon. The light efficiency is enhanced by the reflecting member having an even surface after the first and the second sacrificial layers are formed in order to have even surfaces. In addition, the active matrix, the active layer and the reflecting member have no damages because the second sacrificial layer is removed by using the oxygen plasma or the vapor of bromine fluoride or xenon fluoride and the first sacrificial layer is removed by using the vapor of bromine fluoride or xenon fluoride.

Abstract: Improved trench forming methods for semiconductor substrates using BSG avoid the problems associated with conventional TEOS hard mask techniques. The methods comprise: (a) providing a semiconductor substrate, (b) applying a conformal layer of borosilicate glass (BSG) on the substrate; (c) forming a patterned photoresist layer over the BSG layer whereby a portion of a layer underlying the photoresist layer is exposed, (d) anisotropically etching through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers may be applied over the BSG layer between the BSG layer and the photoresist layer.

Abstract: A semiconductor bare chip includes a plurality of stud bumps provided on the surface of the semiconductor bare chip body, each of the stud bumps including a seat and a head protruding from the seat. A height of the head is less than a thickness of electrodes on said board.

Abstract: A metal layer is patterned by compression moulding using a stamp to create a thickness contrast pattern, followed by etching to transfer the thickness contrast pattern into the entire thickness of the metal layer. The stamp is typically patterned using a technique such as electron beam lithography, and the etchant typically etches through the entire metal layer. The method is used to produce structures such as microelectronic circuits.

Abstract: A fabrication method for a dual damascene structure comprising an air-gap is provided. The method includes forming sequentially a first dielectric layer, a stop layer and a second dielectric layer on a substrate comprising a first metal layer. The first and the second dielectric layers are then defined to form a via. opening exposing the first metal layer and an opening in a predetermined position on the first and second dielectric layers. An oxide layer is then formed on the second dielectric layer covering the opening and forming a gap. The oxide layer and the second dielectric layer are then defined to form a trench, which exposes the first metal layer. A second metal layer and a via plug are then formed in the trench and the via. opening, wherein the second metal layer and the first metal layer are electrically connected through the via plug.

Abstract: A semiconductor device e.g. a gate array, a mask ROM or the like produced by supplementing one or more upper-layer interconnections to units selected out of those previously produced in a half-finished semiconductor device, wherein the upper-layer interconnections are connected exclusively with the selected ones of the foregoing units and are isolated from the unselected ones of the foregoing units, by a space or an insulator layer produced between the upper-layer interconnection and a layer in which conductive paths are produced for connecting the upper-layer interconnection and the foregoing units.

Abstract: Described is a semiconductor photo detector comprising, between a lower electrode and an upper electrode, an optical absorption layer which generates photo carriers, receiving light and an amplification layer which amplifies the photo carriers so generated. In the semiconductor photo detector, the amplification layer is formed of a well layer which causes an avalanche phenomenon and a barrier layer which has a band gap larger than that of the optical absorption layer. The well layer is formed of a crystal substance, by which at the interface with the barrier layer, the energy value of the conduction band of the photo carriers in the well layer is lower than that in the barrier layer and at the same time, the difference in the energy value of the conduction band between the well layer and the barrier layer is larger than the band gap between the valence band and the conduction band of the well layer.

Abstract: A method and apparatus for forming a planar layer on a surface of a microelectronic substrate. The method comprises controlling a temperature of a liquid support material to be at least an annealing temperature of material comprising the planar layer. In one embodiment, the planar layer material has a lower density than the liquid support material and the method further comprises floating the planar layer material upon the liquid support material so that the planar layer material attains a temperature of at least its annealing temperature. The planar layer material forms a planar surface at an interface with the support material and is adhered at an opposite surface to the substrate to form a planar layer thereon. In another embodiment, the planar layer material is adhered to a surface of the substrate.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.