Abstract: The present invention discloses a method for randomizing a microprocessor system, such as an IC card, in order to prevent the microprocessor system from being tampered with. The method ensures that the randomized microprocessor system realizes a functionality equivalent to that of an original microprocessor system and enables easy modification of a configuration of the microprocessor system. In the context of this disclosure, to randomize a microprocessor system means to randomize a microprocessor and a program included in the microprocessor system while maintaining an equivalence of functionality realized by the microprocessor system regardless of this randomization.

Abstract: Instruction branching circuitry including a plurality of logical stacks each having a plurality of entries for storing an address for accessing a corresponding instruction in a memory device. A counter generates a pointer to an entry in an active one of the logical stacks, the counter including incrementation logic incrementing a stored pointer value following a Push operation and decrementation logic decrementing the stored pointer value following a Pop operation to the active one of the logical stacks. Selector circuitry selects the active one of the logical stacks in accordance with the performance of the Push and Pop operations.

Abstract: A circuit is provided to provide instruction streams to a processing device: embodiments of the circuit are appropriate for use with RISC CPUs, whereas other embodiments are useable with other processing devices, such as small processing devices used in a field programmable array. The circuit receives an external instruction stream which provides a first set of instruction values, and has a memory which contains a second set of instruction values. Two or more outputs provide instruction streams to the processing device. The circuit has a control input in the form of a mask which causes a selection means to allocate bits from the first and second sets of instruction values to different instruction streams to the processing device.

Abstract: A processor includes at least one functional unit configured to execute an instruction. The processor also includes an instruction window configured to supply the instruction to the functional unit. The processor further includes a register file configured such that data and a result of execution of the instruction are temporarily stored in the register file. The processor still further includes a branch prediction circuit having a branch execution unit and a branch prediction table. The processor also includes a data value prediction circuit configured to predict a first operand value which will be used by the functional unit and a second operand value which will be used by the branch execution unit to predict a direction of a branch and to store the direction of the branch in the branch prediction table. With such a processor, a branch prediction is made by executing a branch instruction rather than by referring to the history of the branch instruction.

Abstract: A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.

Abstract: A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the vector transfer unit. Program instructions for performing a burst transfer include determining the starting address of the vector data to be transferred, the ending address of the vector data to be transferred, and whether the ending address of the vector data to be transferred is within the same virtual memory page as the starting address. The ending address of the vector data to be transferred is determined based on the number of data elements to be transferred, the stride of the vector data to be transferred, and the width of the vector data elements to be transferred. When the amount of data to be transferred is divisible by a factor of two, the multiplication of the stride and width of the data elements is carried out by shifting.

Abstract: The present invention provides an instruction fetch unit aligner. In one embodiment, an apparatus for an instruction fetch unit aligner includes selection logic for selecting a non-power of two size instruction from power of two size instruction data, and control logic for controlling the selection logic.

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. An instruction (1003) is decoded and accesses a data item in accordance with an address field (1003a). Another instruction (1002) is decoded and accesses a data item in accordance with an address field (1002a); but in a different manner due to an instruction qualifier (1002b). The instruction qualifier is executed in an implicitly parallel manner with the qualified instruction (1002).

Abstract: A method and circuit for digital signal processing. The disclosed method and circuit uses a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory. The beginning and ending of instructions may occur across memory word boundaries. Instructions may contain variable numbers of instruction fragments that cause a particular operation to be performed. The disclosed circuit has a set of three data buses over which data may be exchanged with a register bank and three data memories. Data buses include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Additionally, the disclosed circuit has a register bank that is accessible by at least two processing units. The disclosed circuit further includes an instruction fetch unit that receives instructions of variable length stored in an instruction memory.

Abstract: A method and apparatus for providing a stateless multiplatform instruction set architecture (ISA) for use in a computer system having a processor and memory storing a control program for implementing the invention. The system is used to statelessly execute instructions authored to correspond to a variety of different ISA's on a unitary platform. The ISA of the invention uses a very long instruction word (VLIW) architecture with 64-bit instructions, of which several high-order bits are reserved for an ISA identifier tag. When the processor receives an instruction for execution, it inspects the instruction to determine from the ISA identifier tag to which original, native ISA the instruction corresponds. If the corresponding ISA is the native VLIW ISA for the processor, then the instruction is routed to the instruction dispatch unit of the processor, and thence to at least one functional unit for execution.

Abstract: An ISYNC instruction does not cause a flush of speculatively dispatched or fetched instructions (instructions that are dispatched or fetched after the ISYNC instruction) unconditionally. The present invention detects the occurrence of any instruction that changes the state of the machine and requires a context synchronizing complete; these instructions are called context-synchronizing-required instructions. When a context-synchronizing-required instruction completes, the present invention sets a flag to note the occurrence of that condition. When an ISYNC instruction completes, the present invention causes a flush and refetches the instruction after the ISYNC if the context-synchronizing-required flag is active. The present invention then resets the context-synchronizing-required flag. If the context-synchronizing-required flag is not active, then the present invention does not generate a flush operation.

Abstract: A method of performing a store operation in a computer processor is disclosed. The method issues a store operation that is divided into a pre-fetch micro-operation that loads a needed cache line into a cache memory, and the subsequent store micro-operation stores a data value into the needed cache line that was pre-fetched into the cache memory.

Abstract: A processing system for processing instructions of computer programs utilizes a plurality of pipelines and a control mechanism in order to detect and prevent write-after-write data hazards. The plurality of pipelines receives and processes instructions of a computer program that includes a first instruction and a second instruction. The control mechanism is designed to detect a write-after-write data hazard associated with the first instruction and the second instruction, when the first and second instruction are configured to cause data to be written to the same location. After detecting the write-after-write data hazard, the control mechanism determines whether there is another instruction in the instructions being processed by the pipelines that is dependent on the data produced or retrieved by execution of the first instruction. If there is such an instruction, the control mechanism cancels the first instruction by transmitting a cancellation request.

Abstract: A method and apparatus for generating a unique and reversible human readable number is disclosed. The human readable number is comprised of human readable symbols for representing a specific combination of selected options in differentiated products in built-to-order systems or differentiated services in an overall customized service package. The human readable number preferably represents many possible permutations of available options, which are selectable by a customer. The human readable number maintains its uniqueness and reversibility when the number of options are increased, or when new differentiated products or services are added.

Abstract: In one embodiment of the invention, a processor includes a memory order buffer (MOB) including load buffers and store buffers, wherein the MOB orders load and store instructions so as to maintain data coherency between load and store instructions in different threads, wherein at least one of the threads is dependent on at least another one of the threads. In another embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least another one of the threads, the execution pipeline including a memory order buffer that orders load and store instructions. The processor also includes detection circuitry to detect speculation errors associated with load instructions in a load buffer.

Abstract: The processor is configured to predecode instruction bytes prior to their storage within an instruction cache. During the predecoding, relative branch instructions are detected. The displacement included within the relative branch instruction is added to the address corresponding to the relative branch instruction, thereby generating the target address. The processor replaces the displacement field of the relative branch instruction with an encoding of the target address, and stores the modified relative branch instruction in the instruction cache. The branch prediction mechanism may select the target address from the displacement field of the relative branch instruction instead of performing an addition to generate the target address. In one embodiment, relative branch instructions having eight bit and 32-bit displacement fields are included in the instruction set executed by the processor.

Abstract: A method and system for a compression scheme used with program executables that run in a reduced instruction set computer (RISC) architecture such as the PowerPC is disclosed. Initially, a RISC instruction set is expanded to produce code that facilitates the removal of redundant fields. The program is then rewritten using this new expanded instruction set. Next, a filter is applied to remove redundant fields from the expanded instructions. The expanded instructions are then clustered into groups, such that instructions belonging to the same cluster show similar bit patterns. Within each cluster, the scopes are created such that register usage patterns within each scope are similar. Within each cluster, more scopes are created such that literals within each instruction scope are drawn from the same range of integers. A conventional compression technique such as Huffman encoding is then applied on each instruction scope within each cluster.

Abstract: A computing system includes a viewing screen, user interface means, a plurality of application processes, a data file and agent engine means. The viewing screen displays images. The user interface means enables a user to select and move the images displayed by the viewing screen. Each application process in the plurality of application processes includes command processor means and action processor means. The command processor means receives semantic commands and executes the semantic commands. The action processor means monitors selection and movement of the images on the viewing screen and generates the semantic commands by lexical and syntactical analysis of the selection and movement of the images on the viewing screen. The semantic commands are sent to the command processor for execution. The data file includes first semantic commands executable by a first application process from the plurality of application processes.

Abstract: A processor and method of fetching data within a data processing system are disclosed. According to the method, a first difference between a first load address and a second load address is calculated. In addition, a determination is made whether a second difference between a third load address and the second load address is equal to the first difference. In response to a determination that the first difference and the second difference are equal, a fourth load address, which is generated by adding the third address and the second difference, is transmitted to the memory as a memory fetch address. In an embodiment of the data processing system including a processor having an associated cache, the fourth load address is transmitted to the memory only if the fourth load address is not resident in the cache or the target of an outstanding memory fetch request.

Abstract: A method and apparatus for transitioning a processor from a first mode of operation for processing a first instruction set architecture (instruction set) to a second mode of operation for processing a second set instruction set. The method provides that instructions of a first instruction set architecture (instruction set) are processed in a pipelined processor in a first mode of operation, and instructions of a second, different, instruction set, are processed in the pipelined processor in a second, different, mode of operation. While operating in one mode and before a switch to the other mode occurs, the pipeline is loaded with a set of instructions that transition the processor from one mode to the other, wherein the set of instructions are substantially insensitive to the mode that the processor operates in.