Abstract: In a digital signal processor for pipeline processing divided into at least three steps, i.e., instruction fetch cycle, instruction decode cycle and instruction execution cycle, a value of a register (A) is put on a data bus assuming the condition is consistent when a condition execution instruction is decoded in an instruction decoder (14). Then, in the instruction execution cycle of the condition execution instruction, a register (B) introduced the value on the data bus when upon consistency of the condition. As a result, even before a condition flag (Z) changes as a result of execution of the instruction for generating the condition in the instruction execution cycle, the condition execution instruction can be decoded. Thus, the processor may omit an instruction other than “condition generation instruction or condition execution instruction” which was conventionally required.

Abstract: An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function register, which greatly reduces the volume of data required for configuration. The cell can be cascaded freely over a bus system, the EALU being decoupled from the bus system over input and output registers. The output registers are connected to the input of the EALU to permit serial operations. A bus control unit is responsible for the connection to the bus, which it connects according to the bus register. The unit is designed so that distribution of data to multiple receivers (broadcasting) is possible. A synchronization circuit controls the data exchange between multiple cells over the bus system. The EALU, the synchronization circuit, the bus control unit, and registers are designed so that a cell can be reconfigured on site independently of the cells surrounding it.

Abstract: An apparatus and method for implementing a register free list scheme is provided. An instruction received in an execution unit can be assigned an absolute register number as its destination register. A new physical register tag from a free list can be assigned to the absolute register number and a tag future file can be updated with the new physical register tag. The old physical register tag can be read from the tag future file and stored in a retire queue entry corresponding to the instruction along with the new physical register tag and an architectural register identifier corresponding to the absolute register number. A valid bit corresponding to the entry can be set in response to the entry being written. In response to an abort signal, a swap bit corresponding to the entry can be set, the valid bit can be reset, and the new physical register tag can be conveyed to a rename unit in response to receiving a free register request.

Abstract: A parallel computer of this invention includes a plurality of memory elements and a plurality of processing elements and each of the processing elements is connected to logically adjacent memory elements. For example, the processing elements which corresponds to a logical position (i, j) is connected to the memory elements which correspond to a plurality of logical positions (i, j), (i, j+1), (i+1, j) and (i+1, j+1). It is preferable if each of the memory elements can be accessed from the exterior. According to this invention, efficient memory access can be made and the parallel processing can be performed at high speed without increasing the hardware amount and making the control operation complicated. Further, the operation speed of the image processing can be enhanced by constructing an image memory by use of a plurality of memory elements and causing the processing element to effect the image processing in a distributed and cooperative manner.

Abstract: An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results.

Abstract: An apparatus and method for executing floating-point store instructions in a microprocessor is provided. If store data of a floating-point store instruction corresponds to a tiny number and an underflow exception is masked, then a trap routine can be executed to generate corrected store data and complete the store operation. In response to detecting that store data corresponds to a tiny number and the underflow exception is masked, the store data, store address information, and opcode information can be stored prior to initiating the trap routine. The trap routine can be configured to access the store data, store address information, and opcode information. The trap routine can be configured to generate corrected store data and complete the store operation using the store data, store address information, and opcode information.

Abstract: A specific implementation is disclosed where a backward branch address instruction is fetched at a branch address. The backward branch instruction has an offset value to define the size of a program loop. A counter is set to a value that is proportional to the size of the loop. In one example the counter is set to the offset value. As each instruction of the loop is executed the counter is modified to indicate a remaining number of instructions in the loop. When no instructions remain in the current pass of the loop, the counter is reset to the offset value and the loop is repeated until a termination condition encountered. As part of the implementation the instruction after the branch instruction is read and stored prior to the loop being executed.

Abstract: A device includes a plurality of DSPs, instruction memories respectively provided to the DSPs, a master memory storing download information which is to be written into the instruction memories, and an address generator generating addresses of the instruction memories and the master memories.

Abstract: In one method, a hazard on a register is detected based on the register ID from a latch of a first stage of a processor pipeline. The pipeline is stalled after a stale value of the register is stored in a latch of a later stage of the pipeline. The stale value in the latch is then replaced with a fresh value while the pipeline is stalled.

Abstract: A method and an apparatus for reducing the number of instruction transactions in a microprocessor are disclosed. As a method, the number of issued instructions carried by an issued instruction bus in a computer system are reduced by determining if an instruction fetched by a fetch unit matches a cached instruction tag. When the fetched instruction matches the cached instruction tag, an opcode and an associated instruction corresponding to the cached instruction tag are directly injected to an appropriate function unit. The apparatus includes a plurality of tag PC cache memory devices used to store tag PC entries associated with target instructions injected directly to corresponding function units included microprocessors and the like. The injection reduces the number of instructions fetched from the program memory as well as the number of issued instructions carried by an issued instruction bus.

Abstract: An instruction alignment unit is provided which is capable of routing variable byte length instructions simultaneously to a plurality of decode units which form fixed issue positions within a superscalar microprocessor. The instruction alignment unit may be implemented with a relatively small number of cascaded levels of logic gates, thus accomodating very high frequencies of operation. In one embodiment, the superscalar microprocessor includes an instruction cache for storing a plurality of variable byte-length instructions and a predecode unit for generating predecode tags which identify the location of the start byte of each variable byte-length instruction. An instruction alignment unit is configured to channel a plurality of the variable byte-length instructions simultaneously to predetermined issue positions depending upon the locations of their corresponding start bytes in a cache line.

Abstract: A method and apparatus that adds each one of multiple elements of a packed data together to produce a result. According to one such a method and apparatus, each of a first set of portions of partial products is produced using a first set of partial product selectors in a multiplier, each of the first set of portions of the partial products being zero. Each of the multiple elements is inserted into one of a second set of portions of the partial products using a second set of partial product selectors, each of the second set of portions of the partial products being aligned. Each of the multiple elements are added together to produce the result including a field having the sum of the multiple elements.

Abstract: A dispersal unit in combination with a chain affinity unit and an intra-cycle dependency analyzer routes instructions in a microprocessor in order to improve microprocessor performance. The dispersal unit routes instructions to a particular cluster in the microprocessor in response to information stored in the chain affinity unit. The intra-cycle dependency analyzer identifies dependencies in groups of instructions to the dispersal unit, and the dispersal unit routes instructions in the group based on those dependencies.

Abstract: A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Abstract: In one method, a predicted predicate value may be determined. A predicated instruction is then conditionally executed depending on the predicted predicate value. For example, in accordance with one embodiment of the present invention, a predicate table stores historical information corresponding to a predicate. A pipeline coupled to the table receives a predicted predicate value calculated from the historical information. The pipeline may use this predicted predicate value to conditionally execute a predicated instruction. The actual predicate value is provided back to the predicate table from the pipeline.

Abstract: The present invention generally relates to a hybrid VLIW-SIMD programming model for a digital signal processor. The hybrid programming model broadcasts a packet of information to a plurality of functional units or processing elements. Each packet contains several instructions having certain characteristics, such as instruction type and instruction length, among others. The hybrid programming model includes functional units which are reconfigurable based upon the instructions with an instruction packet and the availability of the functional units. The model groups the functional units such that the operations specified in the instructions can be efficiently executed and selects which functional units should be utilized for a given operation.

Abstract: A bypass mechanism is disclosed for a computer system that executes load and store instructions out of order. The bypass mechanism compares the address of each issuing load instruction with a set of recent store instructions that have not yet updated memory. A match of the recent stores provides the load data instead of having to retrieve the data from memory. A store queue holds the recently issued stores. Each store queue entry and the issuing load includes a data size indicator. Subsequent to a data bypass, the data size indicator of the issuing load is compared against the data size indicator of the matching store queue entry. A trap is signaled when the data size indicator of the issuing load differs from the data size indicator of the matching store queue entry. The trap signal indicates that the data provided by the bypass mechanism was insufficient to satisfy the requirements of the load instruction.

Abstract: A microprocessor detects a floating point exchange instruction followed by a floating point instruction and dispatches the two instructions to the floating point unit as one combined instruction. The predecode unit marks the two instructions as a single instruction. A start bit is asserted for the first byte of the floating point exchange instruction and an end bit is asserted for the last byte of the floating point instruction. The combined instruction is dispatched into the instruction execution pipeline. A decode unit decodes the opcodes of the two instructions and passes the opcode of the floating point instruction to the floating point unit and passes exchange register information to the floating point unit. The exchange register information includes a sufficient number of bits to specify a floating point register and a valid bit.

Abstract: A method for detecting independent predicated instructions comprises associating all instructions within a block of code with true and false bit vectors that have bit locations corresponding to instructions that produce pairs of mutually exclusive predicates. A computation is performed in which the true bit vectors associated with the first and second instructions are EXCLUSIVE-ORed to produce a first result. The false bit vectors associated with the first and second instructions are EXCLUSIVE-ORed to produce a second result. The first and second results are then ANDed to produce a third result. If the third result is a non-zero result, the first and second instructions are independent.

Abstract: In one method, a predicted predicate value for a predicate is determined. A predicated instruction is then conditionally executed depending on the predicted predicate value. For example, in accordance with one embodiment of the present invention, a predicate table stores historical information corresponding to a predicate. A pipeline coupled to the table receives a predicted predicate value calculated from the historical information. The pipeline may use this predicted predicate value to conditionally execute a predicated instruction. The actual predicate value is provided back to the predicate table from the pipeline.