Abstract: Method and apparatus for communicating heterogeneous data traffic simultaneously using a hybrid Code Division Multiplexing (CDM)/Code Division Multiple Access (CDMA)-Time Division Multiplexing (TDM)/Time Division Multiple Access (TDMA) system which communicates data on a per data type basis, rather than a per user or per channel basis. A transmitter accepts a plurality of data streams, each of which includes either Constant Bit Rate Data (CBR) or Variable Burst Rate Data (VBR), where CBR is characterized by a steady data rate and strict latency requirements and VBR is characterized by a variable data rate with large peaks and lulls and loose latency requirements. The system identifies each input data stream as CBR or VBR. CBR data is spread using CDM/CDMA with an appropriate spreading factor for CBR, whereas VBR data is modulated/encoded and interleaved with CDM/CDMA with an appropriate spreading factor for VBR and TDM/TDMA, respectively.

Abstract: The topology of a network is represented, or emulated, by a topology engine comprising processing elements interconnected via a connection matrix. Queries representing physical problems of the network are supplied by a host processor to the topology engine, where they are processed in the processing elements in accordance with the topology to produce responses which are returned to the host processor. In particular, the network can be a communications network and the queries can comprise search requests for determining connection paths between devices of the network. The topology engine can use processors with multiple instances so that it is more compact than the communications network that it represents.

Abstract: A QoS monitoring system and method for a DiffServ-capable network element operable in a trusted domain network such as an ISP network. The network element is organized as a plurality of terminating line cards interconnected via a switch fabric capable of supporting virtual ingress/egress pipes (VIEPs). Buffer queues on the ingress and egress sides of the network element, which are established for supporting traffic flows on individual VIEPs, are monitored for determining QoS parametric information such as throughput, loss, delay, jitter and available bandwidth. A policing structure is operably coupled with a buffer acceptance and flow control module for monitoring traffic behavior on the ingress side. Another buffer acceptance/flow control module and aggregate-level monitoring module are disposed on the egress side of the network element that cooperates with a scheduler which shapes outgoing traffic.

Abstract: A wireless communication network includes a plurality of mobile nodes each including a transceiver, a phased array antenna connected to the transceiver, and a controller connected to the transceiver. The controller schedules a respective semi-permanent time slot for each time frame to establish a communication link with each neighboring mobile node and leaves at least one available time slot in each time frame. Each time frame has up to N semi-permanent time slots and at least 2N?1 available time slots. The controller also schedules the at least one available time slot to also serve the communication link with a neighboring mobile node based upon link communications demand. The phased array antenna is aimed by the controller towards each neighboring mobile node during communication therewith.

Abstract: A system controls transmission of packet flows in a network device on a per-flow basis. The system includes multiple token buckets corresponding to the output ports of the network device, multiple bucket counters associated with the token buckets, and control logic. The token buckets store one or more tokens. Each of the tokens corresponds to a portion of one or more received packet flows to be transmitted by the network device. The bucket counters have one or more programmable counting properties and generate token increment signals for storing tokens in corresponding ones of the token buckets. The control logic monitors the packet flows being sent through the network device and controls the programmable counting properties of the bucket counters based on the monitored packet flows.

Abstract: An integrated circuit processes a communication packet and comprises a core processor and scheduling circuitry. The core processor executes a software application that directs the core processor to process the communication packet. The scheduling circuitry retrieves first scheduling parameters cached in a context buffer for the packet and executes a first algorithm based on the first scheduling parameters to schedule subsequent transmission of the communication packet.