Abstract: A semiconductor device, and a method of fabrication, is introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and a first plurality of bonding pads and a second plurality of bonding pads are formed in the recesses. In an embodiment, the first plurality of bonding pads have a first width and a first pitch, and the second plurality of bonding pads have the first width and are grouped into clusters. The first plurality of bonding pads and the second plurality of bonding pads in the first substrate are aligned to a third plurality of bonding pads in a second substrate and are bonded using a direct bonding method.

Abstract: A phase change memory structure, including a substrate having a cavity extending from a surface of the substrate into an interior region thereof, wherein the cavity is bounded by side wall surface, wherein the cavity is coated on the side wall surface with a film of phase change memory material defining a core that is at least partially filled with dielectric material such as alumina. Such phase change memory structure can be fabricated in a substrate containing a cavity closed at one end thereof with a bottom electrode, by a method including: conformally coating sidewall surface of the cavity and surface of the bottom electrode closing the cavity, with a phase change memory material film, to form an open core volume bounded by the phase change memory material film; at least partially filling the open core volume with alumina or other dielectric material; and forming a top electrode at an upper portion of the cavity.

Abstract: A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures.

Abstract: A method of fabricating an image sensor includes forming a pixel array in an imaging region of a semiconductor substrate and forming a trench in a peripheral region of the semiconductor substrate after forming the pixel array. The peripheral region is on a perimeter of the imaging region. The trench is filled with an insulating material. An interconnect layer is formed after filling the trench with insulating material. A first wafer is bonded to a second wafer. The first wafer includes the interconnect layer and the semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the insulating material. A via cavity is formed through the insulating material. The via cavity extends down to a second interconnect layer of the second wafer. The via cavity is filled with a conductive material to form a via. The insulating material insulates the conductive material from the semiconductor substrate.

Abstract: A TFT array substrate is disclosed. The TFT array substrate includes a TFT area, which includes a TFT first electrode layer, a TFT second electrode layer, a TFT insulation layer, and a TFT etching stop layer. The TFT array substrate also includes also includes a storage capacitor, which includes a capacitor first electrode layer, a capacitor second electrode layer, a capacitor insulation layer, and a capacitor etching stop layer. The TFT first electrode layer and the capacitor first electrode layer are formed in a shared first electrode layer, the TFT second electrode layer and the capacitor second electrode layer are formed in a shared second electrode layer, the TFT insulation layer and the capacitor insulation layer are formed in a shared insulation layer, and the TFT etching stop layer and the capacitor etching stop layer are formed in a shared etching stop layer.

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.

Abstract: Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line in electrical contact with a device. The method further includes forming at least one staple structure in electrical contact with the at least one metal line. The at least one staple structure is formed such that electrical current passing through the at least one metal line also passes through the at least staple structure to reduce electromigration issues.

Abstract: An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit.

Abstract: Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.

Abstract: A layer arrangement in accordance with various embodiments may include: a first layer having a side; one or more nanoholes in the first layer that are open towards the side of the first layer; a second layer filling at least part of the nanoholes and covering at least part of the side of the first layer, the second layer including at least one of the following materials: a metal or metal alloy, a glass material, a polymer material, a ceramic material.

Abstract: A three-dimensional thin-film solar cell comprising a three-dimensional thin-film solar cell substrate having a prism array design comprising a plurality dual-aperture unit cells with emitter junction regions and doped base regions. The three-dimensional thin-film solar cell comprises emitter metallization regions and base metallization regions.

Abstract: The present disclosure provides a complimentary metal-oxide-semiconductor (CMOS) image sensor (CIS) device. In accordance with some embodiments, the device includes a semiconductor region having a front surface and a back surface; a light-sensing region extending from the front surface towards the back surface within the semiconductor region; a gate stack formed over the semiconductor region; and at least one epitaxial passivation layer disposed at least one of over and below the light-sensing region. In some embodiments, the at least one epitaxial passivation layer includes a p-type doped silicon (Si) layer.

Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.

Abstract: A method of manufacturing at least one semiconducting micro- or nano-wire used for formation of an optoelectric structure, optoelectronic structures including the micro- or nano-wires, and a method enabling manufacture of the photoelectronic structures. The method includes providing a semiconducting substrate, forming a crystalline buffer layer on the substrate, the buffer layer having a first zone over at least part of its thickness composed mainly of magnesium nitride in a form MgxNy, and forming at least one semiconducting micro- or nano-wire on the buffer layer.

Abstract: An organic light emitting diode display includes a substrate including a thin film transistor, a plurality of pixels on a pixel area of the substrate, a plurality of auxiliary electrodes between the pixels, an opposite electrode on the pixels and on the auxiliary electrodes, the opposite electrode being electrically connected to the auxiliary electrodes, and including a same material as the auxiliary electrodes, and a power supply electrode on the substrate, the power supply electrode being in a periphery of the pixel area and being configured to supply power to the pixels.

Abstract: A gate cavity is formed exposing a portion of a silicon fin by removing a sacrificial gate structure that straddles the silicon fin. An epitaxial silicon germanium alloy layer is formed within the gate cavity and on the exposed portion of the silicon fin. Thermal mixing or thermal condensation is performed to convert the exposed portion of the silicon fin into a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions. A functional gate structure is formed within the gate cavity providing a finFET structure having a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions.

Abstract: A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a second constituent polymer is formed over the first layer. The first constituent polymer is selectively removed from the copolymer layer. A first region of the first layer corresponding to the selectively removed first constituent polymer is etched. The etching leaves a second region of the first layer underlying the second constituent polymer unetched. A metallization process is performed on the etched substrate, and the first layer is removed from the second region to form an air gap. The method may further comprise depositing a dielectric material within the etched first region.

Abstract: Disclosed is a near UV light emitting device. The light emitting device includes an n-type contact layer, a p-type contact layer, an active area of a multi-quantum well structure disposed between the n-type contact layer and the p-type contact layer, and at least one electron control layer disposed between the n-type contact layer and the active area. Each of the n-type contact layer and the p-type contact layer includes an AlInGaN or AlGaN layer, and the electron control layer is formed of AlInGaN or AlGaN. In addition, the electron control layer contains a larger amount of Al than adjacent layers to obstruct flow of electrons moving into the active area. Accordingly, electron mobility is deteriorated, thereby improving recombination rate of electrons and holes in the active area.

Abstract: A light-emission element assembly includes: a light-emission element; a mold section in which the light-emission element is molded; a pad section protruding from an undersurface of the mold section, and electrically connected to the light-emission element; and a reinforcement section provided in the pad section, and projecting towards a side on which the mold section is provided.