Abstract: A thin film transistor includes a semiconductor layer disposed on a base substrate and including an oxide semiconductor material, a source electrode and a drain electrode, which respectively extend from opposing ends of the semiconductor layer, a plurality of low carrier concentration areas respectively disposed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer, a gate insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating layer.

Abstract: Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. A photoresist layer is patterned to simultaneously define mask elements in the array, interface and periphery areas. The pattern is transferred to an amorphous carbon layer. Spacers are formed on the sidewalls of the patterned amorphous carbon layer. Protective material is deposited and patterned to expose mask elements in the array region and in parts of the interface or periphery areas. Exposed amorphous carbon is removed, leaving free-standing spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which the substrate is etched.

Abstract: A semiconductor device includes an IGBT cell including a second-type doped drift zone, and a desaturation semiconductor structure for desaturating a charge carrier concentration in the IGBT cell. The desaturation structure includes a first-type doped region forming a pn-junction with the drift zone, and two portions of a trench or two trenches arranged in the first-type doped region and beside the IGBT cell in a lateral direction. Each of the two trench portions or each of the two trenches has a wide part below a narrow part. The wide parts confine a first-type doped desaturation channel region of the first-type doped region at least in the lateral direction. The narrow parts confine a first-type doped mesa region of the first-type doped region at least in the lateral direction. The desaturation channel region has a width smaller than the mesa region in the lateral direction, and adjoins the mesa region.

Abstract: A MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer itself arranged on a semiconductor substrate including a lateral field-effect control thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated therefrom by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor.

Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

Abstract: A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.

Abstract: A semiconductor package includes terminals extending from a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. Each terminal includes a first plated section, a second plated section, and a portion of a sheet carrier from which the semiconductor package is built upon, wherein the portion is coupled between the first and second plated sections. Each interconnection routing is electrically coupled with a terminal and can extend planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes at least one intermediary layer, each including a via layer and an associated routing layer. The semiconductor package includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals.

Abstract: A nitride group semiconductor light emitting device includes a nitride group semiconductor layer, and an electrode structure. The electrode structure is arranged on or above the semiconductor layer, and includes a plurality of deposited metal layers. The plurality of deposited metal layers of the electrode structure includes first and second metal layers. The first metal layer is arranged on the semiconductor layer side. The second metal layer is arranged on or above the first metal layer. The first metal layer contains Cr, and a first metal material. The first metal material has a reflectivity higher than Cr at the light emission peak wavelength of the light emitting device. According to this construction, the first metal layer can have a higher reflectivity as compared with the case where the first metal layer is only formed of Cr, but can keep tight contact with the semiconductor layer.

Abstract: A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate.

Abstract: Memory cells and memory cell structures having a number of phase change material gradients, devices utilizing the same, and methods of forming the same are disclosed herein. One example of forming a memory cell includes forming a first electrode material, forming a phase change material gradient on the first electrode material, and forming a second electrode material on the phase change material gradient.

Abstract: A display device includes: a substrate; a signal line on the substrate; a signal input line on the substrate and connected to a driver; a first insulating layer between the signal line and the signal input line; a second insulating layer on the signal line, the signal input line and the first insulating layer; an organic layer on the second insulating layer; a first contact hole defined in the organic layer, the first insulating layer and the second insulating layer and exposing the signal line; a second contact hole defined in the organic layer and the second insulating layer and exposing the signal input line; and a connecting member on the organic layer, and connecting the signal line and the signal input line to each other through the first contact hole and the second contact hole, respectively.

Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.

Abstract: An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit.

Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.

Abstract: A surface of a substrate consists of a plurality of neighboring stripes. Longer edges of the flat surfaces are parallel one to another and planes of these surfaces are disoriented relatively to the crystallographic plane of gallium nitride crystal defined by Miller-Bravais indices (0001), (11-22) or (11-20). The disorientation angle of each of the flat surfaces is between 0 and 3 degrees and is different for each pair of neighboring flat surfaces. The substrate according to the invention allows epitaxial growth of a layered AlInGaN structure by a MOCVD or MBE method which allow to obtain a non-absorbing mirrors laser diode emitting a light in the wavelength from 380 to 550 nm.

Abstract: Methods of fabricating semiconductor devices that include interposers include the formation of conductive vias through a material layer on a recoverable substrate. A carrier substrate is bonded over the material layer, and the recoverable substrate is then separated from the material layer to recover the recoverable substrate. A detachable interface may be provided between the material layer and the recoverable substrate to facilitate the separation. Electrical contacts that communicate electrically with the conductive vias may be formed over the material layer on a side thereof opposite the carrier substrate. Semiconductor structures and devices are formed using such methods.

Abstract: The substrate is made of a compound semiconductor, and has a recess, which opens at one main surface and has side wall surfaces when viewed in a cross section along a thickness direction. The gate insulating film is disposed on and in contact with each of the side wall surfaces. The substrate includes a source region having first conductivity type and disposed to be exposed at the side wall surface; and a body region having second conductivity type and disposed in contact with the source region at a side opposite to the one main surface so as to be exposed at the side wall surface, when viewed from the source region. The recess has a closed shape when viewed in a plan view. The side wall surfaces provide an outwardly projecting shape in every direction when viewed from an arbitrary location in the recess.

Abstract: A light emitting assembly comprising a solid state device coupleable with a power supply constructed and arranged to power the solid state device to emit from the solid state device a first, relatively shorter wavelength radiation, and a down-converting luminophoric medium arranged in receiving relationship to said first, relatively shorter wavelength radiation, and which in exposure to said first, relatively shorter wavelength radiation, is excited to responsively emit second, relatively longer wavelength radiation. In a specific embodiment, monochromatic blue or UV light output from a light-emitting diode is down-converted to white light by packaging the diode with fluorescent organic and/or inorganic fluorescers and phosphors in a polymeric matrix.

Abstract: Disclosed is a method of fabricating a light-emitting diode package, which comprises a light-emitting chip operative to emit light of a first wavelength range. The method comprises the steps of: dispensing a photoluminescent mixture on the light-emitting chip, the photoluminescent mixture being capable of absorbing a portion of light of the first wavelength range emitted from the light-emitting chip to re-emit light of a second wavelength range; partially curing the photoluminescent mixture by heating the photoluminescent mixture to a pre-curing temperature and then cooling the photoluminescent mixture to below the pre-curing temperature; and fully curing the photoluminescent mixture to harden the photoluminescent mixture. An apparatus for fabricating a light-emitting diode package is also disclosed.