Abstract: A method for manufacturing integrated circuit semiconductor device is provided for doping polysilicon formed on an N-well in a semiconductor substrate. Form a silicon oxide layer on the N-well. Then form a blanket polysilicon layer over the silicon oxide layer and pattern the polysilicon layer into a structure. Form a sacrificial oxide layer over the polysilicon structure. Then ion implant .sup.49 (BF.sub.2).sup.+ ions into the N-well and the polysilicon layer forming the source/drain regions and doping the polysilicon layer with P-type dopant thereby forming a doped polysilicon layer from the polysilicon layer. Then etch the sacrificial oxide layer away from the device. Form a polyoxide layer over the polysilicon structure. Then form a silicon oxide layer over the polyoxide layer followed by forming a glass layer thereover.

Abstract: A P-type substrate for infrared photo diodes can be produced by the present invention. A CdZnTe substrate is utilized. A first layer of HgCdTe is formed by liquid phase epitaxy on the substrate. A CdTe passivation layer is formed over the HgCdTe. A ZnS layer is formed over the CdTe layer. A noble metal is introduced into either the CdTe or ZnS layers. During a subsequent baking of the composite, the noble metal diffuses throughout the composite and into the HgCdTe layer.

Abstract: A silicon wafer for the volume production of integrated circuit devices has a lattice network of chip separating structure containing a plurality of rectangular-shaped cavities which is filled completely with silicon single crystals to form single crystal layer sections of the same height as the depth of the lattice network. Both the cavities and the single crystal layer sections are dimensioned to suit the planar dimensions of an integrated circuit device chip to be used for volume production.

Abstract: A process for forming different types of sensors, including metal oxide (10), calorimetric (44), and heterojunction (48), on the same semiconductor chip includes the steps of doping a top surface of a silicon substrate (16) with boron to form a diffusion region (18) for a resistive heater, forming a first silicon nitride layer (24) on the diffusion region, forming a first metal layer (26) on the first silicon nitride layer to provide a resistive temperature detector, forming a second silicon nitride layer (28) on the first metal layer, forming a second metal layer (34) on the second silicon nitride layer, and etching a sensing cavity (40) underneath and adjacent to the diffusion region using an anisotropic wet etchant and the diffusion region as an etch-stop. A metal oxide layer (36) is formed over the second metal layer for a metal oxide or heterojunction sensor. The sensor can optionally be suspended by tethers (38) within the sensing cavity.

Abstract: A method of making an integrated circuit in semiconductor on insulator material and the circuit which comprises providing a semiconductor on insulator structure having a device layer, preferably silicon, and an electrically insulating layer, the device layer being in contact with one surface of the electrically insulating layer. An underlayer is provided which contacts the opposing surface of the electrically insulating layer. The structure is then patterned and trenches are etched to expose a surface of the underlying layer and to form mesas extending from the underlying layer. Ions can now optionally be implanted into selected regions of the underlying layer. A dielectric is provided between the mesas extending to or into the substrate and fabrication of the integrated circuit is then completed. The dielectric can be a thermal oxide at the exposed surface with a dielectric over the thermal oxide.

Abstract: An apparatus for producing thin film coatings and/or dopant levels on semiconductor wafers or other substrates with improved film growth uniformity (of thickness and composition) and/or dopant uniformity is provided. The apparatus is positioned in a furnace tube between the wafers and a gas inlet. The apparatus comprises a conical shaped baffle.

Abstract: An amorphous silicon color detector comprising a structure composed of a transparent conductive oxide film (TCO) layer/an a-Si:H layer/a metal layer, of which the a-Si:H layer is an amorphous silicone layer having a thickness greater than 1 .mu.m, and the metal layer is made of a metals selected from the metal group consisting of Cr, Au, Pd, Al, Pt, Mo, Ag or Ti. A depletion region of the color detector is re-arranged in position and in content thereof according to the absorbencies to different color lights in different bias voltages to achieve the purpose of detecting different color light. An amorphous silicone color image sensor comprises a plurality of the color detectors arranged in linear array incorporated with a scanning device, a processor and an A/D converter to process the signals obtained from scanning. The amorphous silicone color image sensor is especially used in a scanning machine or a fax machine. A manufacture process of the amorphous silicon color detector is also disclosed.

Abstract: In the formation of shallow depth junctions, atoms of inner elements, such as helium, argon, xenon or krypton are implanted at a chosen energy and concentration to create microvoids in the epitaxial layer at a chosen depth. Then, upon implantation of boron ions, the implantation of which creates interstitial silicon atoms, during an anneal step the interstitial atoms fill the voids and determine the junction depth.

Abstract: A Schottky electrode is formed on an n-type SiC base member with an Al--Ti alloy or by laying Al films and Ti films alternately, and a resulting structure is subjected to a heat treatment of 600.degree. C. to 1,200.degree. C. A p-type SiC layer may be formed around the Schottky junction so as to form a p-n junction with the n-type SiC base member.

Abstract: A method for producing Group III nitride films with high indium content and superior optical quality. The Group III nitride film will produce light in the ultraviolet, blue, green, yellow, and red spectral regions. This will enable fabrication of full-color displays and produce a reliable white light source. A metal organic chemical vapor deposition (MOCVD) process in combination with a photochemical process reduces the growth temperature required to produce optical quality Group III nitride films.

Abstract: A semiconductor substrate includes a semiconductor layer, where the density of an impurity is reduced by out diffusion, provided on an insulating layer. In a method for manufacturing such a semiconductor substrate, a semiconductor substrate including a high-density impurity layer at the side of its surface is bonded to another substrate having an insulating layer. Thereafter, the semiconductor substrate is removed, and the impurity density of the remaining high-density impurity layer is reduced by out diffusion.

Abstract: A method for manufacturing shallowly doped semiconductor devices. In the preferred embodiment, the method includes the steps of: (a) providing a substrate where the substrate material is represented by the symbol Es (element of the substrate); and (b) implanting the substrate with an ion compound represented by the symbol E1.sub.x Ed.sub.y, where E1 represents an element having high solubility in the substrate material with minimal detrimental chemical or electrical effects and can be the same element as the substrate element, Ed (dopant element) represents an element which is an electron acceptor or donor having high solubility limit in the substrate material, and x and y indicate the number of respective E1 and Ed atoms in the ion compound.

Abstract: In a method of fabricating semiconductor laser chips using a circular semiconductor wafer, an orientation flat is formed at a part of the peripheral side surface of the semiconductor wafer so that an alignment error of the orientation flat from a crystalline axis of the semiconductor wafer is within.+-.0.04.degree.. Therefore, the processing precision in fabricating semiconductor laser chips using the circular wafer is improved.

Abstract: The present invention provides a method for suppressing transient enhanced diffusion of ion implanted dopants in a semiconductor substrate comprising bombarding the substrate in a vacuum with a beam of bubble-forming ions at a first temperature, a first energy, and a first ion dose sufficient to form a dispersion of bubbles at a depth equivalent to a peak of damage distribution in the substrate from implantation of dopant ions into the substrate in a vacuum at a second temperature, a second energy, and a second ion dose, said dispersion being sufficient to reduce said damage distribution.

Abstract: A solid phase diffusion process using boron silicide film as diffusion source to improve controllability of diffusion of boron impurity into a silicon substrate in order to achieve a shallow junction. The process includes: cleaning the surface of a Si substrate by removing the native oxide film thereof to expose an active surface; treating the active surface to form thereon a boron silicide film as an impurity source; and introducing boron impurity from the boron silicide film into the Si substrate to form a boron diffusion layer. In this manner, a boron diffusion layer having a high surface concentration and a shallow junction can be formed because the boron silicide film is formed directly on the surface of the Si substrate. Because the boron silicide film is chemically and physically stable, an improved diffusion controllability is obtained. The diffusion controllability is further improved by accurately evaluating the impurity film optically during the fabrication process.

Abstract: Epitaxial growth of a chirped superlattice with constant dopings is achieved with minimal growth interruption time. This is done by doping only one of the two compositions during growth of its layer. For example, in the growth of a plurality of alternating layers of InP and GaInAs to form the superlattice, either the InP layers are doped with an n-type dopant, such as silicon, or the GaInAs layers are doped with a p-type dopant, such as beryllium. Alternatively, InP can equally be doped p-type (with beryllium) and GaInAs can be doped n-type (with silicon). In either case, the doping scheme described herein is easily done during molecular beam epitaxial growth by opening and closing the shutter of the dopant (silicon or beryllium) source cell at the appropriate times. To the electrical carriers, the doping superlattice scheme of the present invention presents a uniform doping without any need to change the doping cell temperature.

Abstract: A method of forming apparatus including a force transducer on a silicon substrate having an upper surface, the silicon substrate including a dopant of one of the n-type or the p-type, the force transducer including a cavity having spaced side walls and a diaphragm supported in the cavity, the diaphragm extending between the side walls of the cavity, comprising the steps of: a. implant in the substrate a layer of a dopant of the one of the n-type or the p-type; b. deposit an epitaxial layer on the upper surface of the substrate, the epitaxial layer including a dopant of the other of the n-type or the p-type; c. implant spaced sinkers through the epitaxial layer and into electrical connection with the layer of a dopant of the one of the n-type or the p-type, each of the sinkers including a dopant of the one of the n-type or the p-type; d. anodize the substrate to form porous silicon of the sinkers and the layer; e. oxidize the porous silicon to form silicon dioxide; and f.

Abstract: The aim of the present invention is to obtain a thin-film transistor which has a small OFF current. A film whose main component is aluminum and which will be the gate electrode is formed in an island shape, and a porous oxide layer is formed on its side surfaces by an anodic oxidation process. A source region and a drain region are then formed by performing impurity ion implantation. Further, the aforementioned oxide layer is removed, and lightly doped regions are formed by once again performing impurity ion implantation. In this way it is possible to obtain a construction which has lightly doped regions between the source/drain regions and the channel-forming regions.

Abstract: A method for manufacturing a semiconductor device can reduce a micro-roughness and does not change a construction and electric characteristics of elements formed in the semiconductor device. In the method for manufacturing the semiconductor device including a pre-oxidation process in which an oxide layer is first formed on a silicon wafer, and the oxide layer is secondly eliminated to eliminate impurities on a surface of the silicon wafer, a formation of the oxide layer in the pre-oxidation process is performed in an oxidization atmosphere including H.sub.2 O and gas including germanium hydride (german --GeH.sub.4 --). Since german (GeH.sub.4) is included in the oxidization atmosphere, it is possible to reduce a softening temperature of the silicon dioxide formed in pre-oxidation, thereby decreasing the micro-roughness on the surface of the silicon wafer.

Abstract: A semiconductor light receiving device includes a semiconductor crystal substrate having a principle plane which almost coincides with a crystal face having a low order face orientation index, a light detecting portion, formed on a surface of the semiconductor crystal substrate or inside the semiconductor crystal substrate, for converting incident light into an electric signal, and a light incident region formed on the principle plane of the semiconductor crystal substrate, for guiding light into the light detecting portion. The surface of at least the optical incident region on the principle plane of the semiconductor crystal substrate is an uneven surface constituted by a large number of crystal faces each having a face orientation index having an order higher than that of the crystal face of the semiconductor crystal substrate.