Abstract: A capped MMIC and method of making same wherein a polymer layer cast over the surface of a semiconductor wafer and vias are formed in the polymer layer down to the wafer surface. The exposed surface of the polymer layer is then metallized and etched in a predetermined pattern to provide a metal pattern over the upper surface of the polymer layer which extends into the vias and to the surface of the wafer. Pads of the metallization are also provided on the upper surface of the polymer layer which are individually electrically isolated from the remainder of the metallization. The wafer is now ground back and backside metallization and other desired processing then takes place in standard manner to complete fabrication of the individual MMICs on the wafer. The MMICs are then diced in standard manner. The MMICs can be secured in a housing fabricated of ceramic or metal. The housing has a plurality of cavities, each cavity for receipt of a MMIC or MMICs.

Abstract: Piezo-optical pressure sensitive devices employing porous semiconductor material as a stress sensitive member. The devices monitor pressure or force applied thereto by detecting a corresponding change in the amount of light absorbed by a porous layer of semiconductive material such as silicon. A pressure or stress signal is thus converted into an optical one. The sensing element of an optical switch embodiment of the device is comprised of a transparent layer of material upon which there is disposed a porous layer of semiconductive material. When unstressed, the porous layer absorbs monochromatic light of a predetermined wavelength. When the porous layer is stressed, a metallized epitaxial layer formed thereon reflects the light back through the transparent layer where it can be detected by a light detection system.

Abstract: An SOI/DI IC chip including a handle wafer in the form of a section of silicon substrate contiguous with the layer of insulation beneath the silicon slice containing the device regions separated by trenches filled with low-conductivity polysilicon dielectric. One of the trenches is etched through the layer of insulation, and the polysilicon in that trench is doped to provide desired electrical conductivity to establish electrical contact with the handle wafer. Metallization is applied over the top of this one trench to make possible electrical connection to the handle wafer from above the chip by use of conventional wiring techniques.

Abstract: A method for suppressing boron penetration in a PMOS with a nitridized polysilicon gate includes steps of 1) growing a layer of gate oxide on a substrate, 2) forming at least one first polysilicon layer on the gate oxide layer, 3) nitridizing the first polysilicon layer, 4) forming a second polysilicon layer on the first polysilicon layer; and 5) implanting B-containing ions into the first and second polysilicon layers for constructing a PMOS structure wherein the nitridizing step suppresses a boron ion from penetration into the substrate. The present invention is characterized in nitridation on a polysilicon gate instead of a gate oxide which can effectively suppress boron penetration, avoid drawbacks resulting from nitridizing a gate oxide, and moreover, improve the reliability of the device owing to the slight nitridation effect in the polysilicon gate and the gate oxide.

Abstract: A protective device for an integrated circuit and the manufacturing method thereof is disclosed in which a floating well is formed in a substrate by implanting first conductivity-type impurity into the substrate. The substrate is a second conductivity-type substrate. A diffusion resistor is formed in the well by implanting second conductivity-type impurity into the well. The diffusion resistor has a first terminal to be connected electrically to the driving circuit stage and a second terminal to be connected electrically to the driven circuit stage. A grounded region is formed in the well around the diffusion resistor by implanting second conductivity-type impurity into the well, and by applying a ground reference voltage to the grounded region.

Abstract: A method of fabricating a semiconductor device incorporates the steps of forming in succession a gate insulting film, a polycrystalline silicon film and a first insulating film on a semiconductor substrate surface, and etching a portion of the first insulating film, the polycrystalline silicon film and the gate insulating film to expose the semiconductor substrate. The exposed semiconductor substrate is etched to form a trench. The trench is then buried by depositing a second insulating film and thereafter a third insulating film. The second and third insulating films are then etched with the third insulating film being etched at a higher rate than the second insulating film. The polycrystalline silicon film is used as a stopper to leave behind the second and third insulating films in the trench. A fourth insulating film is deposited, and then etched again using the polycrystalline silicon film as a stopper. The side walls of the trench are thus coated with the fourth insulating film.

Abstract: Method for laying at least one semiconductive plate with a specific thickness and size on a support, wherein it includes the following stages: the bombardment by ions of one face of a semiconductive substrate so as to create there a film of gaseous microbubbles along a splitting plane of the substrate, the ion implantation energy being provided so as to obtain the film of gaseous microbubbles at a depth corresponding to the specific thickness of the semiconductive plate, the ions being selected from rare gas or hydrogen gas ions, the rendering integral on the face of the substrate of the support, illuminating by a laser beam of the zone of the face of the substrate corresponding to the plate to be placed through the support, the luminous energy transmitted by the beam through the support needing to be sufficient so as to induce in the corresponding region of the film of gaseous microbubbles a temperature sufficient to cause splitting of the plate of the support and provoke increasing of the adherence of the p

Abstract: A method and apparatus for forming semiconductor particles (42) for solar cells using an optical furnace (30). Uniform mass piles (26) of powered semiconductor feedstock are almost instantaneously optically fused to define high purity semiconductor particles without oxidation. The high intensity optical energy is directed and focused to the semiconductor feedstock piles (26) advanced by a conveyer medium (16) thereunder. The semiconductor feedstock piles (26) are at least partially melted and fused to form a single semiconductor particle (42) which can be later separated from a refractory layer (18) by a separator (50), preferably comprised of silica. The apparatus (10) and process is automated, providing a high throughput to produce uniform mass, high quality spheres for realizing high efficiency solar cells. The apparatus is energy efficient, whereby process parameters can be easily and quickly established.

Abstract: After forming a gate oxide film on the surface side of a single crystalline silicon substrate, a first polycrystalline silicon layer is subsequently formed. After that, portions of polycrystalline silicon layers are left in each gate electrode formation region of a high voltage drive circuit. Then, the gate oxide film in a low voltage drive circuit side is removed while maintaining this state. Then, after forming a gate oxide film on those surface sides, a polycrystalline silicon layer is subsequently formed in the surface side. After that, impurities are introduced into the polycrystalline silicon layer to provide it with electrical conduction, and then portions of polycrystalline silicon layers are left.

Abstract: On the substrate of an integrated circuit chip is deposited a first insulating layer in which a low resistivity semiconductor region is subsequently formed. An insulating film is formed on a side wall of the low resistivity semiconductor region. A slit is formed in the first insulating layer so that a portion of the substrate and a portion of the insulating film are exposed. First, second and third semiconductor layers of different conductivity types are epitaxially grown in the slit so that the second layer is in contact with the exposed insulating film. A second insulating layer is deposited on the chip. Through the second insulating layer first, second and third electrodes are brought into contact with the first and third semiconductor layers and with the low resistivity semiconductor region. Due to the stacking of epitaxial layers of different conductivity types, the impurity profiles of the epitaxial layers can be precisely controlled.

Abstract: Four electric field containment regions are formed in a semiconductor substrate by implanting ions into the substrate along four axes that are angularly oriented about a normal to a surface of the substrate in four orthogonal directions respectively. The implant axes are further angularly tilted from the normal by a large angle on the order of 45.degree. such that the axes intersect the normal at a point below the surface. A field effect transistor (FET) is formed in the substrate above the containment regions such that the FET is substantially centered about the normal and has a channel that is aligned with one of the four orthogonal directions. A source and drain are formed at opposite ends of the channel. The containment regions formed under the source and drain respectively are configured to contain electric fields extending therefrom and thereby suppress punchthrough. The four containment regions are implanted at angles that minimize channeling, and any channeling that does occur is symmetrical.

Abstract: A method of screening a semiconductor device. A silicon wafer having gate electrodes formed on the gate oxide film is prepared. An insulating layer is deposited on the silicon wafer. Gate electrode portions of a group of transistors to be tested are exposed. A conductive layer is deposited on the silicon wafer having exposed gate electrodes. The conductive layer is patterned to be a wiring layer so that the gate electrodes of a group of the transistors can be electrically connected to each other. The chip area to be tested is irradiated with light having intensity enough to generate a required quantity of carriers in a depletion layer between a well and a substrate. A predetermined test voltage is applied between the wiring layer and the substrate of the silicon wafer during irradiation of the light to measure current flowing through the wiring layer and the gate oxide film. An abnormality of the gate oxide film can be detected on the basis of the measured current value.

Abstract: The trap-state density of a switching transistor of a picture element is reduced by selectively treating only the switching transistor of the picture element part of a liquid display with the plasma hydrogenation treatment, the laser annealing treatment or both thereof. That is, aluminum is sputtered before making an aperture for a contact hole of a thin layer transistor, then a mask aluminum is formed on the active circuit element forming region by patterning only aluminum on the picture element forming region. Then, the plasma hydrogenation treatment is made, and the mask aluminum film is removed by the etching. Following the similar process thereafter, an active circuit integrated liquid crystal display is fabricated. Thereby, the leakage current of the switching transistor of the picture element part can be reduced and decrease of pressure tolerance of transistors constituting the active circuit element and the depletion can be prevented.

Abstract: A method for forming a transparent conductive film includes the steps of: forming an ITO film on a substrate by sputtering a target including oxygen atoms, indium atoms, and tin atoms under an inert gas atmosphere; patterning the ITO film by selectively removing a prescribed portion of the ITO film using an etching method; and doping the patterned ITO film with oxygen using an ion shower doping method, thereby forming the transparent conductive film from the ITO film.

Abstract: A ferroelectric capacitor structure is designed for fabrication together with MOS devices on a semiconductor substrate. The ferroelectric capacitor includes a diffusion barrier above the surface of the substrate for preventing the materials of the ferroelectric capacitor from contaminating the substrate or MOS devices. The ferroelectric capacitor comprises a bottom electrode, a thin film ferroelectric layer and a top electrode. An interlayer dielectric is formed to cover portions of the ferroelectric thin film and provide an opening therethrough for the top electrode. A ferroelectric memory cell comprises a field effect transistor together with a ferroelectric capacitor fabricated on a semiconductor substrate. In one configuration, the ferroelectric capacitor is offset from the field effect transistor, while in another configuration, the ferroelectric capacitor is substantially above the field effect transistor to provide greater density.

Abstract: A process for producing a semiconductor substrate, including the phases of implanting oxygen ions into a semiconductor silicon substrate through one surface thereof to form a high oxygen concentration layer in the semiconductor silicon substrate, and then heat-treating the semiconductor substrate to cause a chemical reaction to occur between the implanted oxygen ions and the silicon, thereby forming an insulating silicon oxide film in the semiconductor silicon substrate, wherein the heat treatment phase includes at least a heat treatment step using an atmosphere having an oxygen partial pressure of 5.times.10.sup.3 Pa or more.

Abstract: A wafer bonding method for forming a SOI structure comprising the steps of bringing wafers into proximity in a state with one wafer a slight, substantially uniform clearance away from the other wafer and pressing one point of at least one wafer of the two wafers against the other wafer. In another aspect of the invention, there is provided a method of positioning for photolithography using an alignment mark portions and/or a vernier portions formed on a SOI substrate, which comprises the step of removing semiconductor layer portions corresponding to the alignment mark portions and/or the vernier portions. In further another aspect of the invention, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a new pattern of a strage node formed longitudinally along a word line. Further, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a unique strage node having a conductive side wall.

Abstract: A wafer design and dicing technique for creating semiconductor chips from wafers. A succession of oxide layers are deposited in first and second regions of a surface of a silicon substrate. The regions are separated by a street having no oxide layers therein, and the successive oxide layers form a vertical wall with a surface normal to the surface of the silicon substrate. A shock-absorbent material is deposited in the street, forming a concave meniscus therein. The shock-absorbent material retards the trajectories of silicon particles set into motion when the wafer is diced into chips.

Abstract: Hydrogenation of an optical device that includes an intrinsic region and at least one associated doped region is effective to improve the photoresponsivity of the device. Subsequent annealing of the device substantially restores the conductivity of the doped region(s) while preserving in the intrinsic region a major part of the beneficial effects of hydrogenation.

Abstract: A process for fabricating devices is disclosed. Numerous devices are formed on a substrate. The substrate is then placed on an adhesive tape mounted on a dicing ring. The devices are then separated into individual chips by dicing the substrate. Prior to dicing, the substrate is coated with a material that is relatively insoluble in water. After the substrate is diced, the coating is removed by rinsing the substrate with an organic solvent in which the material is substantially soluble. The organic solvent dissolves the coating but does not dissolve the adhesive on the tape or otherwise adversely effect the adhesion between the tape and the substrate.