Abstract: An object of the present invention is to provide a highly reliable semiconductor device that allows voids remaining in a bonding material to be reduced. The semiconductor device includes a semiconductor chip, an insulation substrate, a metal base plate, a resin section, and a bump. The semiconductor chip is warped into a concave shape. On the insulation substrate, the semiconductor chip is mounted by bonding. The metal base plate has the insulation substrate mounted thereon and has a heat dissipation property. The resin section seals the insulation substrate and the semiconductor chip. The bump is disposed in a joint between the semiconductor chip and the insulation substrate. A warp amount of the semiconductor chip warped into a concave shape is equal to or greater than 1 ?m and less than a height of the bump.

Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.

Abstract: In one embodiment, a method for creating a forecasting model for a multiple-imaging unit DLT is disclosed. A stage of the DLT is positioned so that a set of alignment marks provided on a substrate are placed under a set of the DLT's eyes. For each alignment mark in the set, a first image is acquired using a camera coupled to the eye above it at a first time, and a first position of the alignment mark is obtained within the camera's FOV from the first image, to determine a first measured position. One or more additional images of the alignment mark are subsequently obtained at subsequent times, and one or more corresponding subsequent measured positions are determined. Differences between sequential ones of the measured positions are respectively calculated, a forecasting model to correct for eye center drift of the set of eyes is created, and corrections digitally applied.

Abstract: A semiconductor device package includes a circuit layer, an antenna structure, a first encapsulant and a reflector. The circuit layer has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The antenna structure is disposed within the circuit layer. The first encapsulant is disposed on the first surface of the circuit layer, the first encapsulant having a surface. The reflector is disposed on the first encapsulant. The third surface of the circuit layer is substantially coplanar with the surface of the first encapsulant.

Abstract: A wafer-level system-in-package structure and an electronic apparatus are provided. The wafer-level system-in-package structure includes a substrate having a plurality of first chips formed therein. A first chip is formed by being grown on the substrate through a semiconductor process. The wafer-level system-in-package structure also includes an encapsulation layer having a plurality of second chips embedded therein. The encapsulation layer covers the substrate and the first chips. At least one of the plurality of second chips is electrically connected to at least one of the plurality of first chips through a conductive bump, and electrically-connected first and second chips have an overlapping portion.

Abstract: Apparatuses and methods for gate power to circuits of semiconductor devices are described. An example apparatus includes a substrate, a first wiring and a second wiring, and a plurality of transistors. The first wiring may be supplied with a power voltage, and the first wiring is formed over the substrate and is elongating in a first direction. The second wiring may be formed between the substrate and the first wiring, and vertically overlapping the first wiring with the second wiring elongating in the first direction. The plurality of transistors are vertically coupled between the first wiring and the second wiring.

Abstract: An electronic component device includes an electronic component embedded in a resin structure and including a portion exposed on a first main surface of the resin structure, first wiring lines extending from the first main surface of the resin structure to the electronic component and electrically connected to the electronic component, second wiring lines on a side of a second main surface of the resin structure and electrically connected to respective connection electrodes that are electrically connected to the first wiring lines, and low-elastic modulus layers at a height position between the first wiring lines and the exposed portion of the electronic component in respective regions in which the first wiring lines straddle boundaries between the resin structure and the electronic component, having elastic moduli lower than those of the first wiring lines, and made of a conductive material.

Abstract: A semiconductor device includes: a mounting member having an electrode; a conductive member facing the electrode; and a bonding member electrically and mechanically connecting the electrode and the conductive member. The bonding member is made of a sintered body in which an additive particle including a metal atom having aggregation energy higher than a silver atom is added to an silver particle.

Abstract: A semiconductor device includes an insulative substrate, a wiring pattern, a bonding portion, and a semiconductor element. The wiring pattern is formed on an upper surface of the insulative substrate. The bonding portion is formed on an upper surface of the wiring pattern. The semiconductor element includes an electrode pad connected to an upper surface of the bonding portion. The bonding portion includes first sintered layers distributed in the bonding portion and a second sintered layer having a density differing from each of the first sintered layers and surrounding the first sintered layer.

Abstract: There is provided a technique that includes: (a) providing a substrate having a film containing a predetermined element, oxygen and carbon formed on a surface of the substrate; and (b) modifying at least a surface of the film by supplying a carbon-free fluorine-based gas to the substrate under a condition in which etching of the film does not occur.

Abstract: A semiconductor device includes a semiconductor substrate, at least two first films, a bridge portion, and a conductive member. The two first films are spaced apart from each other, along a first direction which is an in-plane direction of the semiconductor substrate, and along a second direction which is in the in-plane direction of the semiconductor substrate and is perpendicular to the first direction. The bridge portion connects portions of side facing surfaces of the two first films to each other, and has a flat bottom surface. The conductive member is provided under the bottom surface of the bridge portion.

Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.

Abstract: There is provided a semiconductor-bonding resin composition having excellent thermally conductive property and electrically conductive property and suitable for joining a power semiconductor element and an element support member. There are provided: a semiconductor-bonding resin composition containing (A) a bismaleimide resin including an aliphatic hydrocarbon group on a main chain, (B) a curing agent, (C) a filler containing electrically conductive particles having a specific gravity of 1.1 to 5.0, and (D) silver microparticles having an average particle size of 10 to 300 nm; a semiconductor-bonding sheet obtained using the semiconductor-bonding resin composition; and a semiconductor device including a semiconductor joined by the semiconductor-bonding sheet.

Abstract: A semiconductor apparatus includes: a substrate including a circuit pattern on an upper surface side and a metal plate on a lower surface side; a semiconductor device joined to the circuit pattern via a conductive component; a case located to surround the substrate; a sealing material sealing the semiconductor device and the substrate in a section surrounded by the case; and a bonding agent bonding the case and the metal plate on a side face of the substrate.

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

Abstract: A metal member includes a metal substrate and a porous metal layer. A composite includes the metal member and a resin member. The metal substrate has one surface, is made of a metal material, and has a region formed as an uneven layer having an uneven shape with respect to the one surface. The porous metal layer has a mesh-like shape and is formed on the uneven layer. The uneven layer includes a plurality of protrusions protruding in a direction normal to the one surface.

Abstract: Provided is a semiconductor module comprising: a semiconductor chip; a cooling portion having a refrigerant passing portion through which a refrigerant passes; and a laminated substrate having: a first metal interconnection layer; a second metal interconnection layer; and an insulation provided between the first metal interconnection layer and the second metal interconnection layer, wherein the cooling portion has: a top plate; a bottom plate; and a plurality of protruding parts which are provided on a surface of the bottom plate, and are separated from each other in a flow direction of the refrigerant, and are respectively provided continuously in a direction orthogonal to the flow direction, wherein the plurality of protruding parts are provided at a position overlapping with one end of the second metal interconnection layer and at a position overlapping with the semiconductor chip in the flow direction.

Abstract: The present application provides a flexible display panel and a manufacturing method thereof. The flexible display panel includes a flexible substrate, a buffer layer formed on the flexible substrate, and a metal layer formed on the buffer layer. The flexible display panel includes a display area and a bending area in a lateral direction. The buffer layer includes a first portion and a second portion, the first portion corresponding to the display area, the second portion corresponding to the bending area, and the thickness of the second portion is less than the thickness of the first portion.

Abstract: Some embodiments include a semiconductor package. The semiconductor package has a semiconductor die with a primary region which includes integrated circuitry, and with an edge region which includes a portion of an alignment mark location. The portion of the alignment mark location includes a segment of an alignment mark. The alignment mark includes a pattern of lines and spaces, with the lines extending along a first direction. The portion of the alignment mark location also includes a texture having a pattern other than lines extending along either the first direction or along a second direction substantially orthogonal to the first direction. Some embodiments include methods for alignment marking semiconductor wafers.