Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.

Abstract: A stack of layers providing an ohmic contact with the semiconductor, a lower metal layer of the stack is disposed in direct contact with the semiconductor; and a radiation absorption control layer disposed over the lower layer for controlling an amount of the radiant energy to be absorbed in the radiation absorption control layer during exposure of the stack to the radiation during a process used to alloy the stack with the semiconductor to form the ohmic contact.

Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.

Abstract: A power semiconductor device and package includes multiple electrically parallel semiconductor device legs designed to share source regions and share a drain region between two devices in each leg laterally staggered from each other to distribute thermal conductivity across the shared source regions. A multitude of jigsaw patterned lateral isolation trenches are formed in a substrate of the device. The trenches are configured to isolate the laterally staggered line-in and line-out source regions from a common drain region of the plurality of semiconductor device legs. The staggered devices are also designed for staggered time and staggered heat conductivity delays and current spreading from the package input to an output of a respective pair of devices to improve current and heat conductivity from the package input to an output of a subsequent pair of devices.

Abstract: The disclosed subject matter provides thin films including a metal silicide and methods for forming such films. The disclosed subject matter can provide techniques for tailoring the electronic structure of metal thin films to produce desirable properties. In example embodiments, the metal silicide can comprise a platinum silicide, such as for example, PtSi, Pt2Si, or Pt3Si. For example, the disclosed subject matter provides methods which include identifying a desired phase of a metal silicide, providing a substrate, depositing at least two film layers on the substrate which include a first layer including amorphous silicon and a second layer including metal contacting the first layer, and annealing the two film layers to form a metal silicide. Methods can be at least one of a source-limited method and a kinetically-limited method. The film layers can be deposited on the substrate using techniques known in the art including, for example, sputter depositing.

Abstract: Voids within metal deposited on interconnect structures are filled with cobalt or a cobalt compound to enhance electromigration performance. A reflow process to enlarge interconnect metal grain size is performed prior to filling the voids. An interconnect metal microstructure beneath the filled voids includes grain boundaries extending to the bottom portions of the voids. A coating of manganese atoms provides resistance to electromigration. Copper interconnects having fine dimensions and improved reliability are obtained.

Abstract: A single chip integrated circuit (IC) package includes a die pad, and a spacer ring on the die pad defining a solder receiving area. A solder body is on the die pad within the solder receiving area. An IC die is on the spacer ring and is secured to the die pad by the solder body within the solder receiving area. Encapsulating material surrounds the die pad, spacer ring, and IC die. For a multi-chip IC package, a dam structure is on the die pad and defines multiple solder receiving areas. A respective solder body is on the die pad within a respective solder receiving area. An IC die is within each respective solder receiving area and is held in place by a corresponding solder body. Encapsulating material surrounds the die pad, dam structure, and plurality of IC die.

Abstract: An electronic device may include a semiconductor package, that may include a package substrate. The package may include a semiconductor die. A plurality of package interconnects may include a first pillar extending from a surface of the package substrate. The electronic device may include a socket that may be configured to couple with the semiconductor package. The socket may include a plurality of socket interconnects configured to engage with the package interconnects. The plurality of socket interconnects may include a first contact, and the first contact may include an arm. The arm of the first contact may be configured to engage with the first pillar, and the arm may be configured to laterally displace when engaged with the first pillar. The engagement of the arm with the first pillar may establish an electrical communication pathway between the semiconductor package and the socket.

Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.

Abstract: The light-emitting apparatus comprising thin film transistors and light emitting elements, comprises; a second inorganic insulation layer on a gate electrode, a first organic insulation layer on the second inorganic insulation layer, a third inorganic insulation layer on the first organic insulation layer, an anode on the third inorganic insulation layer, a second organic insulation layer overlapping with the end of the anode and having an inclination angle of 35 to 45 degrees, a fourth inorganic insulation layer on the upper and side surfaces of the second organic insulation layer and having an opening over the anode, an organic compound layer in contact with the anode and the fourth inorganic insulation layer and containing light-emitting material, and a cathode in contact with the organic compound layer, wherein the third and the fourth inorganic insulation layers comprise silicon nitride or aluminum nitride.

Abstract: A method for forming a semiconductor device includes: providing a structure having a first stop layer formed above a substrate, a first dielectric layer formed on the first stop layer, a second stop layer formed on the first dielectric layer, and conductive lines formed in the first dielectric layer and spaced apart from each other; forming a first dummy layer on the second stop layer; patterning the first dummy layer to form a first patterned dummy layer; forming a second dummy layer on the first dummy layer to form a first trench; etching back the second dummy layer and the first patterned dummy layer to form a second trench, wherein the second trench is self-aligned with the first trench. The second trench extends downwardly to the first dielectric layer and forms an opening at the second stop layer.

Abstract: A semiconductor device includes metal layers, first dummy conductive cells, and groups of second dummy conductive cells. The metal layers include empty areas and are grouped into pairs of neighboring metal layers. The first dummy conductive cells are each formed in each of the empty areas in each of the pairs of neighboring metal layers that is overlapped by another empty area or a line in the same pair of neighboring metal layers. Each group of the second dummy conductive cells is formed in each of the empty areas in each of the pairs of neighboring metal layers that is overlapped by a signal line in the same pair of neighboring metal layer.

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductor, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductor is electrically connected to the source drain structure. The protection layer is present between the conductor and the first spacer and on a top surface of the first gate structure.

Abstract: An electronics package is disclosed that comprises a multilayer interconnect structure including a plurality of insulating substrate layers each having a plurality of microvias formed therein, a plurality of conductive wiring layers positioned on the plurality of insulating substrate layers, and a plurality of conductive microvias in the plurality of microvias to, wherein a bottom wiring layer includes a plurality of first terminal pads that are positioned on a bottom surface of the multilayer interconnect structure. The electronics package also comprises an electrical component coupled to the bottom surface of the multilayer interconnect structure, the electrical component including first I/O pads aligned with the first terminal pads and second I/O pads aligned to regions of the multilayer interconnect structure without first terminal pads.

Abstract: A method for manipulating ions contained in an encapsulation material for a semiconductor device is provided. The method includes processing the encapsulation material and applying an electric field to the encapsulation material before the encapsulation material is finally cured. The ions contained in the encapsulation material have a mobility that decreases as the encapsulation material cures. By applying the electric field to the encapsulation material before the encapsulation material is finally cured, the amount of ions contained in the encapsulation material is reduced and/or the ions contained are concentrated in one or more regions of the encapsulation material. Corresponding apparatuses and semiconductor packages manufactured by the method are also described.

Abstract: A semiconductor package device is provided that includes a first circuit layer having a first conductive layer and a first stud bump and a second circuit layer having a second conductive layer and a second stud bump. The first stud bump has a first portion and a second portion, and the second portion of the first stud bump is electrically connected to the second conductive layer. The second stud bump has a first portion and a second portion, and the second portion of the second stud bump is electrically connected to the first conductive layer. The first stud bump partially overlaps the second stud bump in a direction substantially perpendicular to the first circuit layer.

Abstract: A method for forming a metal silicide layer, a semiconductor device and a method for fabricating the device are disclosed. Through depositing a buffer layer between a metal layer and a substrate, metal atoms in the metal layer will diffuse, during a thermal annealing process, through the buffer layer into the substrate while being buffered by the buffer layer. As a result, the diffusion speed and depth of the metal atoms in the substrate are both reduced, and a reaction between the metal and silicon in the substrate is hence slowed down. In this way, the risk of agglomeration of the resulting metal silicide can be effectively lowered, avoiding pinhole defects occurring in the substrate and improving the interface roughness of the resulting metal silicide layer.

Abstract: A method for fabricating a semiconductor chip is disclosed. In an embodiment, the method includes providing a plurality of semiconductor chips, wherein each semiconductor chip comprises a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on a carrier with the second main faces facing the carrier and applying an encapsulation material by transfer molding thereby forming the semiconductor chip panel, wherein the encapsulation material is applied so that the side faces of the semiconductor chips are covered with the encapsulation material while the first main faces are not.