Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.

Abstract: This invention relates to thermosetting resin compositions useful for fluxing underfill applications, particularly in the form of a preapplied film.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a chip, a molding compound, and a dielectric layer. The chip has a connector thereon. The molding compound encapsulates the chip, wherein a surface of the molding compound is substantially lower than an active surface of the chip. The dielectric layer is disposed over the chip and the molding compound, wherein the dielectric layer has a planar surface, and a material of the dielectric layer is different from a material of the molding compound.

Abstract: A method of fabricating a 3D fan-out structure for an integrated circuit device includes providing a substrate carrier having first and second opposing surfaces and an aperture extending between the first and second surfaces. A first semiconductor die is bonded to the first surface of the substrate carrier such that the first die covers the aperture of the substrate carrier. An encapsulant and a second die are deposited within the aperture of the substrate carrier such that an active surface of the second die is exposed and coplanar with the second surface of the substrate carrier. One or more redistribution layers are then applied on the second surface of the substrate carrier to form a 3D fan-out structure.

Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals.

Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

Abstract: A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method includes forming a contact pad over a semiconductor device. A passivation material is formed over the contact pad. The passivation material has a thickness and is a type of material such that an electrical connection may be made to the contact pad through the passivation material.

Abstract: A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.

Abstract: Methods of forming stacked die assemblies are described. Those methods/structures may include forming a circuit element on a first substrate, wherein a first die is adjacent the circuit element, forming a via disposed directly on a surface of the circuit element, and forming a mold compound on the first die, on the circuit element and on the via, wherein the via and circuit element are completely embedded within the mold compound. A routing layer is formed on a top surface of the mold compound, and a second die is coupled with the routing layer.

Abstract: A component-mounted resin substrate includes a thermoplastic resin substrate and an electronic component. The resin substrate includes a surface including a mounting land conductor and a reinforcing resin member. A bump of the electronic component is joined to the mounting land conductor by ultrasonic joining. The reinforcing resin member is in contact with a side surface of the mounting land conductor and has a height smaller than a height of the mounting land conductor.

Abstract: A method of producing a semiconductor device includes forming a stack including a semiconductor material having a Group III nitride semiconductor material formed on a growth substrate, a protective layer formed over the Group III nitride semiconductor material, and a handle layer and a stressor layer formed over the protective layer. The stack is spalled to separate the growth substrate from the stack.

Abstract: Provided herein are mixed resin systems and the use thereof for wafer-level underfill (WAUF) for three-dimensional TSV packages. In one aspect, there are provided compositions comprising (1) an epoxy resin, (2) a maleimide, nadimide or itaconamide, (3) an acrylate and (4) a filler. In certain aspects, the epoxy resin is a siloxane-modified resin. In certain aspects, the invention relates to underfill films prepared from invention compositions. In certain aspects, the invention relates to articles comprising the underfill films described herein.

Abstract: A power semiconductor device and package includes multiple electrically parallel semiconductor device legs designed to share source regions and share a drain region between two devices in each leg laterally staggered from each other to distribute thermal conductivity across the shared source regions. A multitude of jigsaw patterned lateral isolation trenches are formed in a substrate of the device. The trenches are configured to isolate the laterally staggered line-in and line-out source regions from a common drain region of the plurality of semiconductor device legs. The staggered devices are also designed for staggered time and staggered heat conductivity delays from the package input to an output of a respective pair of devices to be shorter than a time and heat conductivity delay from the package input to an output of a subsequent pair of devices.

Abstract: A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.

Abstract: A microelectromechanical microphone includes: a substrate; a sensor chip, integrating a microelectromechanical electroacoustic transducer; and a control chip operatively coupled to the sensor chip. In one embodiment, the sensor chip and the control chip are bonded to the substrate, and the sensor chip overlies, or at least partially overlies, the control chip. In another embodiment, the sensor is bonded to the substrate and a barrier is located around at least a portion of the sensor chip.

Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.

Abstract: A semiconductor package includes a first semiconductor die, a first encapsulant, a first redistribution layer, a second encapsulant and a patterned conductive layer. The first encapsulant encloses the first semiconductor die and has a top surface and a lateral surface. The first redistribution layer is disposed on the top surface of the first encapsulant and electrically connected to the first semiconductor die, wherein a portion of the first redistribution layer is exposed from the lateral surface of the first encapsulant. The second encapsulant covers the first encapsulant and the first redistribution layer. The patterned conductive layer is disposed on at least one of the lateral surface of the first encapsulant or a lateral surface of the second encapsulant, and is electrically connected to the first redistribution layer.

Abstract: Methods of fabricating semiconductor devices and Radio Frequency (RF) components are provided. The method includes providing a circuit layout on a semiconductor layer and providing one or more sacrificial connections to connect bump pads in the circuit layout. The method also includes testing the circuit layout using the one or more sacrificial connections and removing at least a portion of the one or more sacrificial connections. In this way, the performance of the semiconductor device is improved by reducing or avoiding capacitive or inductive leakage paths that can be caused by leftover materials.