Patents Examined by Saleha R. Mohamedulla
  • Patent number: 7125639
    Abstract: A method for the fabrication of patterned devices, in which a latent image is initially formed in a photosensitive material on a carrier, and the exposed material containing the latent image is physically transferred to a substrate before processing. Physical transfer is enhanced by the appropriate selection of coating surface properties and additional coating layers, and by processing steps, such as heating and UV exposure, to promote adhesion to the substrate and detachment from the carrier.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: October 24, 2006
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventor: Charles Daniel Schaper
  • Patent number: 7122281
    Abstract: To print sub-wavelength features on a wafer, a mask set including a full phase PSM (FPSM) and a corresponding trim mask can be used. Phase assignments on the FPSM can result in some feature definition with the trim mask, particularly in non-critical areas. Unfortunately, this limited feature definition can cause significant critical dimension (CD) variations in these non-critical areas. Undesirable critical dimension (CD) variations can be better controlled, even with substantial mask misalignment, by defining multiple feature edge portions with the trim mask in non-critical areas, such as T-intersections, elbows, and other types of intersecting lines.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: October 17, 2006
    Assignee: Synopsys, Inc.
    Inventor: Christophe Pierrat
  • Patent number: 7049033
    Abstract: Absorber material used in conventional EUVL reticles is eliminated by introducing a direct modulation in the complex-valued reflectance of the multilayer. A spatially localized energy source such as a focused electron or ion beam directly writes a reticle pattern onto the reflective multilayer coating. Interdiffusion is activated within the film by an energy source that causes the multilayer period to contract in the exposed regions. The contraction is accurately determined by the energy dose. A controllable variation in the phase and amplitude of the reflected field in the reticle plane is produced by the spatial modulation of the multilayer period. This method for patterning an EUVL reticle has the advantages (1) avoiding the process steps associated with depositing and patterning an absorber layer and (2) providing control of the phase and amplitude of the reflected field with high spatial resolution.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: May 23, 2006
    Assignee: The EUV LLC
    Inventors: Daniel G. Stearns, Donald W. Sweeney, Paul B. Mirkarimi
  • Patent number: 7029800
    Abstract: A static resistant reticle comprises a substrate and a patterning layer and is covered by an antistatic conductive film of quaternary amine (R4N)+Cl?. A pellicle structure comprising an optically transparent membrane tightly stretched on a frame is also coated by an antistatic electro conductive film of a similar material. The reticle with the pellicle form a shielded structure isolating the reticle from ESD.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: April 18, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co Ltd
    Inventors: Wei-Yu Su, Dong-Hsu Cheng, Li-Kong Turn
  • Patent number: 7018746
    Abstract: A method of verifying the placement of sub-resolution assist features (SRAFs) in a photomask layout is described. SRAFs are added to the photomask layout to enhance the process window for semi-isolated and isolated features. Rules are provided to automatically place the SRAFs into the layout. When deficiencies are detected in the assist feature design or in the automated SRAF placement program, the placement of SRAFs requires verification. The method verifies the correct placement by defining a unique image property linked to the accurate placement of the assist features, and combines it with in-situ image simulation of the individual layout.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: March 28, 2006
    Assignee: International Business Machines Corporation
    Inventors: Yuping Cui, Rama Nand Singh
  • Patent number: 7014963
    Abstract: A reticle or mask for use in projecting a circuit pattern, having a transparent substrate with a reflective or dielectric layer thereon. An opaque or blocking layer is placed over the reflective layer. The opaque layer then has a predetermined circuit pattern etched therein. In one embodiment, the opaque layer and the reflective layer are the same size. In another embodiment, the opaque layer has a size larger than the reflective layer. This permits the opaque layer to be adjacent the substrate, which is advantageous when projection optics having a high numerical aperture are used. The reticle of the present invention has particular advantage when using source wavelengths of between 157 nanometers and 365 nanometers. The reflective layer or land has a reflectance greater than chrome, and preferably greater than sixty percent. Therefore, the reflective layer greatly reduces reticle warm-up and thermal distortion.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: March 21, 2006
    Assignee: ASML Holding N.V.
    Inventor: Andrew W. McCullough
  • Patent number: 7011936
    Abstract: A method for structuring photoresists and a corresponding photolithography mask utilize a principal structure and an auxiliary structure. In addition to the principal structure to be imaged, the photomask has an imaging auxiliary structure, which improves the imaging of the principal structure. The portions of the imaging auxiliary structure in the photoresist are exposed in a second exposure step and thereby likewise changed into a form that is soluble in a developer. Only the principal structure remains on the substrate after development.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: March 14, 2006
    Assignee: Infineon Technologies AG
    Inventors: Christoph Nölscher, Armin Semmler, Günther Czech
  • Patent number: 7011926
    Abstract: Within a charged particle beam exposure method for forming a patterned resist layer there is employed separating at least one adjacent pair of fractured pattern elements employed in forming a contiguous latent pattern within a blanket resist layer a gap. By employing the gap, a patterned resist layer formed incident to development of the blanket resist layer is formed with enhanced pattern fidelity and enhanced critical dimension control.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: March 14, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Ren-Guey Hsieh
  • Patent number: 7011909
    Abstract: A photolithography mask is based on a combination of a half-tone phase mask and an alternating phase mask such that, when the radiation passes through some of the openings, a phase difference is in each case produced between adjacent openings, and the surroundings of the openings are partially transparent and shift the phase of the radiation. Consequently, the advantages of alternating phase masks and half-tone phase masks can be realized on one mask and, accordingly, significantly enlarged process windows for the actual lithography process result with the photolithography mask according to the invention. In particular, these advantages can be obtained with only one absorber material, and the size of non-imaging auxiliary structures is approximately as large as the smallest main structure. In addition, the invention provides methods for fabricating the photolithography masks according to the invention.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: March 14, 2006
    Assignee: Infineon Technologies AG
    Inventor: Christoph Noelscher
  • Patent number: 7008731
    Abstract: A method of manufacturing a photomask includes determining dimensions of a pattern in a photomask, determining an exposure latitude on the basis of the dimensions of the mask, and judging if the photomask is defective or non-defective on the basis of whether or not the exposure latitude falls within a prescribed exposure latitude. The pattern in the photomask includes dimensions of critical pattern portions in which an exposure latitude is low.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: March 7, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Nojima, Osamu Ikenaga
  • Patent number: 7008738
    Abstract: A method of formulating and fabricating a mask pattern and resulting mask for forming isolated or closely spaced contact holes in an integrated circuit. The mask has a transparent mask substrate and patterned regions of attenuating phase shift material and opaque, partially transmissive or transparent material arranged to reduce the effect of side lobes and improve depth of focus. The rims, frames and outrigger patterns for the attenuating phase shift material and opaque, partially transmissive or transparent material are determined according to calculations performed on a processor with imaging software for various optical conditions and exposed feature criteria.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: March 7, 2006
    Assignee: Micron Technology, Inc.
    Inventors: H. Daniel Dulman, William A. Stanton
  • Patent number: 7008730
    Abstract: An attenuating phase shifting mask for forming contact holes in a layer of negative resist, a method of forming the mask, and a method of forming the contact holes are described. The mask is formed from a mask blank having a layer of attenuating phase shifting material formed on a transparent mask blank. The attenuating phase shifting material has a transmittance of greater than 20% and between about 20% and 50% for light having a wavelength of 193 nanometers. The mask is a dark tone mask having mask elements formed of the attenuating phase shifting material at the locations of the mask corresponding to the locations of the contact holes. The mask is used to expose a layer of negative resist which is then developed to form the contact holes.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: March 7, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Cheng-Ming Lin
  • Patent number: 7008729
    Abstract: First of all, a substrate applied in the lithography process is provided, and then a high transmission attenuate layer (HTAL) is formed on the substrate. Then an opaque layer is formed on the high transmission attenuate layer (HTAL), and then an ion-implanting process is performed in the high transmission attenuate layer (HTAL). Afterward, the opaque layer is etched to define a first phase region and a second phase region on the high transmission attenuate layer (HTAL). Subsequently, a photoresist layer is formed on the second phase region and the opaque layer to expose a partial surface of the high transmission attenuate layer (HTAL) that is located the first phase region. Then the partial surface of the high transmission attenuate layer (HTAL) that is located on the first phase region is etched through until a predetermined depth in the substrate.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: March 7, 2006
    Assignee: Winbond Electronics Corporation
    Inventors: Kao-Tsair Tsai, Chii-Ming Shiah, Yu-Cheng Tung
  • Patent number: 7005216
    Abstract: Providing a photo mask for KrF excimer laser lithography, which can be produced with high accuracy and low defects in a smaller number of steps. A photo mask for KrF excimer laser lithography according to the present invention is one in which a resist pattern 18 efficiently absorbing a KrF excimer laser light (wavelength: about 248 nm) is formed directly on a quartz substrate 10. The resist pattern 18 comprises: an aqueous alkali-soluble resin having a high light shielding property, which incorporates a naphthol structure having at least one hydroxyl group bound to a naphthalene nucleus; or a radiation sensitive resist having, as a main component, an aqueous alkali-soluble resin containing a derivative of the above-mentioned aqueous alkali-soluble resin as a resin matrix.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: February 28, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Shiraishi, Sonoko Migitaka, Takashi Hattori, Tadashi Arai, Toshio Sakamizu
  • Patent number: 7005215
    Abstract: A mask fabrication and repair technique including multiple exposures is provided. In this multiple exposure technique, the first exposure can define the critical dimensions (CDs) of the shapes for the mask. A subsequent exposure can eliminate isolated defects and significantly reduce the size of defects proximate to the desired shapes on the mask. Because similar processes (i.e. forming, exposing, and developing a photoresist layer) are used for creating and repairing the mask, certain repair-related defects, such as phase and transmission defects, can be minimized. Wafer repair can also be performed using the same multiple exposure technique.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: February 28, 2006
    Assignee: Synopsys, Inc.
    Inventor: Christophe Pierrat
  • Patent number: 7001692
    Abstract: A method of forming a mask comprises forming a mask layer including nitrogen, forming a photoresist pattern on the mask layer and etching the mask layer using a mixes gas including a first gas adapted for etching the mask layer and a second gas for increasing selectivity of the photoresist pattern, thereby forming a hard mask. In this manner, selectivity of the photoresist is improved while a high etching ratio of the nitride layer is maintained when forming a hard mask.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: February 21, 2006
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Sung-Un Kwean, Jae-Seung Hwang
  • Patent number: 7001695
    Abstract: A method and apparatus for improving resolution in photolithography. The method includes steps of mapping a first phase onto a first mask, mapping a second phase onto a second mask, and mapping a trim onto the first mask or second mask (or both). Specifically, the first mask may include Phase1 mapped to 0/180 phase, and the second mask may include Phase2 and trim mapped to 0/180 phase. A set of masks consistent with the foregoing is provided.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: February 21, 2006
    Assignee: LSI Logic Corporation
    Inventors: Ebo H. Croffie, Christopher Neville
  • Patent number: 7001693
    Abstract: A method of forming a photolithographic mask layout with Sub-Resolution Assist Feature (SRAF) elements on a mask for correcting for proximity effects for a pattern imaged comprising the steps of developing a layout of mask features for printing main pattern features. Provide a table of SRAF element data including spacing of main pattern features and SRAF elements, applying SRAF elements to the mask layout as a function of spacing of main pattern features and SRAF elements, legalizing the SRAF elements as a function of style options, and providing a target pattern comprising a modified layout for the mask, identifying problem edge segments of an SRAF element of the target pattern at risk of causing a printing defect, applying a selected bias to the problem edge segments to modify the pattern where there are areas of SRAF element loss, and providing an output of a modified pattern with modified SRAF elements removing the areas of SRAF element loss.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: February 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Lars W. Liebmann, Richard A. Ferguson, Allen H. Gabor, Mark A. Lavin
  • Patent number: 6998203
    Abstract: An extreme ultraviolet lithography mask may be heated locally to change its reflectivity and to adjust for proximity and other optical disturbances. The localized heating may result in the formation of silicide at the molybdenum silicon interface in the multilayer stack that makes up the extreme ultraviolet lithography mask.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: February 14, 2006
    Assignee: Intel Corporation
    Inventor: Pei-Yang Yan
  • Patent number: 6984474
    Abstract: The present invention is directed to a reticle barrier system that prevents contaminants from landing on a mask within lithographic systems using extreme ultra violet light. In particular, a reticle barrier system is provided that consists of a mask barrier and a set of contact barriers. The mask barrier surrounds a mask formed on a reticle, while the contact barriers are affixed between the mask and contact spots on a reticle. The barriers have a height relative to the mask, and different geometries are provided. Collectively, the mask and contact barriers reduce the number of contaminants landing on a mask surface without the use of a pellicle. In an alternate embodiment, the reticle barrier system includes only a mask barrier. Similarly, in another alternate embodiment, the reticle barrier system includes only contact barriers.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: January 10, 2006
    Assignee: ASML Holding N.V.
    Inventors: Stephen Roux, Richard Lenox