Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

Abstract: Methods and apparatus for accessing dispersed storage error encoded data in a dispersed storage network (DSN). For each available primary storage unit, a processing module issues a write slice request including a slice name and encoded data slice corresponding to the primary storage unit where the encoded data slice includes an information dispersal algorithm (IDA) index of the primary storage unit. For each unavailable primary storage unit, the processing module issues a write imposter slice request to a foster storage unit that includes a slice name corresponding to foster storage unit and an imposter encoded data slice corresponding to the unavailable primary storage unit, where the imposter encoded data slice includes an IDA index corresponding to the unavailable primary storage unit. When the unavailable primary storage unit becomes available, the processing module facilitates transfer of the imposter encoded data slice to the newly available primary storage unit.

Abstract: A transmission apparatus includes an encoder that codes a data sequence with a parity check matrix, wherein the data sequence includes a final information bit sequence and virtual information bits, and outputs the final information bit sequence and a parity sequence, as LDPC codes, and a transmitter that transmits the LDPC codes as a transmission data. A column length of the parity check matrix is longer than a total length of the final information bit sequence and the parity sequence, by a length of the virtual information bits that are set to “0” and are not transmitted. The total length of the final information bit sequence and the parity sequence has a sequence length corresponding to a length from a first column to a determined column of the parity check matrix. The encoder generates the LDPC codes by using the first column to the determined column among one or more column(s) of the parity check matrix.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: SISO decoding of a reception signal having a scrambled symbol arrangement is realized using a process having reduced complexity. Coordinates are generated for a reference point obtained by scrambling and mapping a symbol number not a symbol reference point position. This reference point simulates transmission-side scrambling and is generated for each symbol number by a first mapping unit. Because the binary expression of a corresponding original signal number is retained, a bit likelihood calculation unit can easily calculate a bit likelihood based on the distance between the reference point and a reception signal. The calculated bit likelihood is then deinterleaved and subjected to SISO error-correcting decoding. The thus obtained bit likelihood is then reinterleaved and used to calculate a symbol probability. Soft symbols are generated through the multiplication of all the calculated symbol probabilities by corresponding reference points output by a second mapping unit similar to the first mapping unit.

Abstract: In one embodiment, it is proposed a method for storing input data on a set of DNA strands, said input data being represented in a numeral system. This method is remarkable in that it comprises: formatting said input data into a set of blocks of data, each block of data having a size inferior to a size of one DNA strand; applying a first encoding with an erasure code on said set of blocks of data, defining a first set of modified blocks of data, each modified block of data having a size inferior to a size of one DNA strand; applying a second encoding using an error correcting code on each modified block of data of said first set, defining a second set of modified blocks of data, each modified block having a size inferior to a size of one DNA strand; encoding each modified block of data of said second set into a nucleotides block sequence; generating a set of DNA strands, each DNA strand comprising a nucleotides block sequence obtained through said encoding.

Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.

Abstract: An optical transmission technique includes receiving data for transmission over the optical communication network, applying a three-dimensional (3D) error correction code to the data using three component codes, resulting in error correction coded signal, modulating the error correction coded signal using a quadrature amplitude modulation (QAM) scheme and processing and transmitting the modulated signal over the optical communication medium.

Abstract: A storage management computing device obtains an information lifecycle management (ILM) policy. A data protection scheme to be applied at a storage node computing device level is determined and a plurality of storage node computing devices are identified based on an application of the ILM policy to metadata received from one of the storage node computing devices and associated with an object ingested by the one of the storage node computing devices. The one of the storage node computing devices is instructed to generate one or more copies of the object or fragments of the object according to the data protection scheme and to distribute the object copies or one of the object fragments to one or more other of the storage node computing devices to be stored by at least the one or more other storage node computing devices on one or more disk storage devices.

Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.

Abstract: A method for execution by a processing system of a dispersed storage network includes receiving first slices encoded via a first information dispersal algorithm (IDA) in a response to an access request corresponding to an associated data object and determining when a number of the first slices is less than a read threshold corresponding to the first IDA and that the data object is also encoded into second slices via a second IDA. If so, the processing system identifies missing slices encoded via the first IDA corresponding to the access request; determines at least one of the second slices encoded via the second IDA corresponding to the missing slices; retrieves the at least one of the second slices; and generates the data object based on the first slices encoded via the first IDA and the at least one of the second slices encoded via the second IDA.

Abstract: An integrated circuit (IC) device including a first memory device, a second memory device stacked with the first memory device, and one or more memory controllers configured to detect a first error in data stored in the first memory device at a first physical location in the IC device, and upon detecting the first error, determine whether there is a second error in data stored in the second memory device in a second physical location in the IC device near the first physical location.

Abstract: A built-in self-test (BIST) system comprising repair logic structured to share state logic of failed memories across local registers located in a shared registry which services multiple memories, wherein each of the local registers is associated with a different memory.

Abstract: A system includes a transmitting device and a receiving device, wherein the transmitting device is configured to transmit a data group including a plurality of data blocks, each of the plurality of data blocks includes a first error check code, and the data group includes a second error check code, and the receiving device is configured to, based on the second error check code, determine whether an error is present in the data group, when it is determined that the error is present in the data group, determine, based on the first error check code, in which data block of the plurality of data blocks the error is present, and when the error is present in a first data block of the plurality of data blocks, transmit, to the transmitting device, a request for retransmission of the first data block among the plurality of data blocks.

Abstract: Embodiments herein describe the design of a scan cell within an integrated circuit. The scan cell operates in either a test mode or a normal functional mode according to a scan enable signal. The scan cell comprises delay logic including a plurality of delay elements, e.g., a plurality of transistors. The delay logic activates the delay elements only when the scan cell operates in the test mode. The delay elements are activated to change a scan latency of the scan cell. The scan latency of the scan cell is increased to mitigate or prevent hold violations.

Abstract: An electronic device for finding error locations in a codeword includes a plurality of power control units configured to find error locations in the codeword. The plurality of power control units are coupled in parallel. Each of the plurality of power control units includes a plurality of corresponding input control circuits to individually turn on or off the corresponding power control unit.

Abstract: A control circuit receives the mode signals supplied from a mode register and a read enable signal READ supplied from a control logic circuit, which activates enable signals EN1 to EN3 based on the mode signals and read enable signal. For example, the read enable signal READ is activated when a read command is issued from the controller. One mode signal can indicate an operation mode in which a multi-purpose register is used, and another mode signal can indicate an operation mode in which the data bus inversion function is used. When a data masking operation is disabled and an error check operation is enabled, the mode register activates a protection signal SEL. When the data masking operation is enabled or the error check operation is disabled, the protection signal SEL is deactivated. The operation of a deserializer is controlled by clock signals and the protection signal SEL.

Abstract: A wireless device may include processing circuitry that is configured to process a first portion of a packet, the first portion of the packet comprising a legacy signal (L-SIG) field, and determine whether a constellation of a field of a second portion of the packet is binary phase shift keying (BPSK) or quaternary binary phase shift keying (QBPSK). The processing circuitry may be further configured to: process the second portion of the packet in accordance with a packet structure indicated by the constellation.

Abstract: Systems, apparatuses and methods may provide for recording, if a non-volatile memory (NVM) location satisfies an open circuit condition, open circuit location information associated with the NVM location. Additionally, a shift of one or more bits may be conducting during a write of a codeword to the NVM location to avoid open circuit in the NVM location. Moreover, an end of a parity portion of the codeword may be punctured by an amount of the shift. In one example, the end of the parity portion includes a last circulant of the codeword.

Abstract: A coding method with differentiated protection to protect, with a different protection efficiency, a number of groups of data in a frame to be transmitted. The invention is based for that on the use of a correcting code of the LDPC type concatenated with an algebraic correcting code. The invention also proposes a decoding method compatible with the coding method with differentiated protection.