Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

Abstract: A memory controller circuit is disclosed. The memory controller circuit is coupled to an external memory device. The memory controller circuit selectively generates error-correction information for a user input. The selection is based on whether the user input is one of predefined inputs. In order to facilitate that, the memory controller circuit includes a command processor circuit and a memory circuit. The error-correction information is stored within the memory circuit located within the memory controller circuit. Selectively generating the error-free correction information may significantly reduce the amount of memory storage that is required within the memory controller circuit.

Abstract: A correctable memory error may be identified at a first address within a memory device. Based on at least the identifying, a first correctable memory error count may be updated from a first quantity to a second quantity. The second quantity may be determined to exceed or not exceed a threshold. In response to the determining, the first correctable memory error count of the second quantity may be: converted to a third quantity and reported to a host device accordingly, reported to a host device, or not reported to a host device.

Abstract: A method for implementing erasure coding, including identifying a plurality of storage units, determining a number of storage unit failures to be tolerated, organizing data within the plurality of storage units as a matrix of rows and columns for computing one or more parity data, configuring the matrix to include one or more additional rows having preset values, computing the one or more parity data from the matrix that corresponds to the number of storage unit failures to be tolerated, wherein the one or more parity data comprises a row parity, a first diagonal parity, and a second diagonal parity, wherein the one or more additional rows having the preset values are used to compute the first diagonal parity and the second diagonal parity; and wherein the first diagonal parity comprises a different slope from the second diagonal parity.

Abstract: Communication apparatus includes a PHY interface, which is configured to receive over a communication link and to decode a sequence of symbols arranged in a series of data blocks. The PHY interface includes an error correction circuit, which when actuated, corrects errors in decoded data symbols using FEC symbols in the data blocks. The decoded data include data packets containing respective error detection codes. A memory buffers the data blocks received by the PHY interface. A data link layer interface receives the data packets from the PHY interface, checks the data packets using respective error detection codes, and upon detecting an error in a given data packet, signals the PHY interface to read from the memory at least one buffered data block that contains the given data packet while actuating the error correction circuit to correct the error using the FEC symbols in the at least one buffered data block.

Abstract: A method of encoding data in a data block includes generating a first XOR parity from an XOR of all data bits in the data block and an XOR of all row parities of all rows in the data block besides a last row, storing the first XOR parity in the last row, and generating a second XOR parity from an XOR of all column parities of all columns in the data block and an XOR of a parity of the last row.

Abstract: The present invention provides a method of transmitting broadcast signals. The method includes, formatting, by an input formatting block, input streams into plural PLPs (Physical Layer Pipes); encoding, by an encoder, data in the plural PLPs; time interleaving, by a time interleaver, the encoded data in the plural PLPs, wherein the time interleaving includes: cell interleaving, by a cell interleaver, the encoded data by permuting cells in a FEC (Forward Error Correction) block in the plural PLPs; frame mapping, by a framer, the time interleaved data onto at least one signal frame; and waveform modulating, by a waveform block, the mapped data in the at least one signal frame and transmitting, by the waveform block, broadcast signals having the modulated data.

Abstract: A system for providing data encoding includes: an encoder configured to encode message data with an encoding parity-check matrix having a parity part that is in lower-triangular form to generate an encoded message data, the encoded message data being for decoded by a decoder; wherein the encoding parity-check matrix is based on a decoding parity-check matrix that does not comprise any degree-1 node in a parity part of the decoding parity-check matrix; and wherein the system further comprises a non-transitory medium for storing the encoding parity-check matrix, wherein the non-transitory medium is a part of the encoder or is communicatively coupled to the encoder.

Abstract: A method and an apparatus for transmitting and receiving a packet in a broadcasting and communication system are provided. The method includes splitting a source packet block including source packets into a plurality of source packet subblocks, converting the source packet subblocks to source symbol subblocks, respectively, generating a plurality of first repair symbol blocks by encoding the source packet subblocks using a first error correction code, configuring an error correction source packet by adding a source error correction payload IDentifier (ID) to source symbols included in the source symbol subblocks and configuring an error correction repair packet by adding a repair error correction payload ID to repair symbols included in the first repair symbol subblocks, and transmitting the error correction source packet and the error correction repair packet.

Abstract: A technique for providing end-to-end error detection coding between a requesting module and a memory module have been disclosed. A method includes translating a first logical address of a memory request to a physical address. The method includes translating an error control code and data associated with the memory request between a first format and a second format. The error control code and data having the first format is generated based on the first logical address. The error control code and data having the second format is generated based on a second address. The method includes generating an error indicator based on the error control code, the data, and one of the first logical address and the second address.

Abstract: Memory devices and systems having an array of memory cells arranged in a plurality of sectors and a plurality of ECC coverage areas, and control circuitry configured to adjust a size of one or more of the ECC coverage areas.

Abstract: System, methods, and apparatus are described that facilitate transmission/reception of data over a multi-line parallel bus. In an example, the apparatus transmits data bits over a parallel bus includes determining from a prior bus state, a plurality of free wires in the bus for a current bus state, where each free wire satisfies a crosstalk-avoidance constraint in the current bus state for all values of a bit transmitted on the free wire. The apparatus may encode a plurality of data bits using a crosstalk avoidance encoder to obtain a CAC-encoded word, compute an error detection or correction code for the CAC-encoded word, assign bits of the error detection or correction code to the plurality of free wires for transmission during the current bus state, and assign the CAC-encoded word to unassigned wires of the bus for transmission during the current bus state.

Abstract: According to one general aspect, an apparatus may include a memory and a reconfigurable error correction array. The memory may be configured to store data. The reconfigurable error correction array may be configured to provide a plurality of levels of error correction to the memory based, at least in part, upon a number of errors detected within the memory.

Abstract: A data processing apparatus including a processor and a memory has a parity/ECC encoder circuit and a parity/ECC decoder circuit. The parity/ECC encoder circuit is disposed in a signal path for writing data to the memory, includes a parity generating circuit for generating a parity of a plurality of bits from data to be written, and writes the generated parity together with the data into the memory. The parity/ECC decoder circuit is disposed in a signal path for reading data from the memory and includes a parity check unit. The parity generating circuit is configured so that each of a plurality of bits configuring the data contributes to generation of a parity of at least two bits. Consequently, the parity check unit can detect a two-bit error at high speed.

Abstract: A method of encoding a data word in a physical coding sublayer before serial transmission is provided, where data words comprising data bits are received, and the data words encoded using one or more 8B/10B encodings to generate 8B/10B transmission characters. ECC check bits are then generated, and the transmission characters and ECC check bits DC balanced prior to shuffling the bits together to form an encoded word to be transmitted. A receiver may decode by implementing a decode process with error correction. In some embodiments 26 data bits from two 13-bit word are encoded into a 40-bit encoded word. Bits of two or more encoded words may be interleaved for transmission, or multiple copies of encoded words sent. An integrated circuit serializer/deserializer comprises hardware to perform encoding and/or decoding. A hardware functional verification system may also implement the disclosed encoding/decoding for interconnections between emulation chips.

Abstract: A system may include a first device, a second device, a third device, and a serial link between the second device and the third device. The first device may be configured to deliver to the second device an information stream having a transmission fault tolerance associated with a transmission by the second device to the third device over the serial link. A related method may include, during the transmission over the serial link, phases for synchronization between the second and third devices, and during each synchronization phase, the first device may continue to deliver the information stream to the second device.

Abstract: A trellis coded modulator and method for generating an encoded word from an input word. The TCM has a first logic branch configured to generate a data portion of the encoded word; and a second logic branch, coupled in parallel with the first logic branch, and configured to generate a corresponding parity portion of the encoded word sequentially after the generation of the data portion of the encoded word.

Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

Abstract: In general, techniques are described for performing track-error-correcting code on data. A hard drive comprising a storage device and a read channel may be configured to perform the techniques. The read channel may be configured to read data from a track comprising a plurality of data sectors each comprising a plurality of bits, and a parity sector comprising a plurality of parity bits, wherein the data includes a plurality of bit groups, each bit group including a single bit from each data sector, and wherein each parity bit corresponds to a respective bit group, perform a track parity check, and, responsive to determining that the data includes an error, identify one or more data sectors as possible sources of the at least one error and adjust a log-likelihood ratio for at least one bit from the bit group.

Abstract: Classifying memory errors may include accessing data from a location within a memory array of a memory device. The memory array may include at least one bit field to store memory error classification information. One or more memory errors in the data may be determined. One or more memory errors may further be classified. In response to the classifying, memory error classification information may be stored as one or more bit values within the bit field.