Abstract: An apparatus, system, and method for testing packet-based semiconductor devices by using simplified test data packets. Simplified test data packets are generated by conventional memory testers in one format. The simplified test data packets are realigned to another, different format by test mode circuitry located on an integrated circuit chip, test interface, or tester prior to testing the memory device. The test method potentially reduces the number of pieces of data which must be generated using an algorithmic pattern generator on a per-pin basis. Furthermore, the test method potentially reduces the number of packet words that has a combination of data generated from an APG and vector memory. Packet-based semiconductor devices are also disclosed.

Abstract: A testing system evaluates one or more integrated circuit chips using RF communication. The system includes an interrogator unit with a radio communication range, and an IC chip adapted with RF circuitry positioned remotely from the interrogator unit, but within the radio communication range. The interrogator unit transmits a power signal to energize the IC chip during test procedures, and interrogating information for evaluating the operation of the IC chip. Test results are transmitted by the IC chip back to the interrogator unit for examination to determine whether the IC chip has a defect. In this is manner, one or more IC chips can be evaluated simultaneously without physically contacting each individual chip.

Abstract: A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pair of I/O lines for each array which are, in turn, coupled to a pair of complementary data lines. The data lines are coupled to respective inputs of a DC sense amplifier, one of which is provided for each array. A multiplexer connects the pair of I/O lines for either one of the arrays to the data lines in a normal operating mode. Thus, in the normal operating mode, data are selectively coupled to the inputs of the DC sense amplifier from the complementary digit lines for an addressed column. In a test mode, the multiplexer connects the I/O lines for both arrays to the data lines to compress the data from the two arrays.

Abstract: A system for testing both simulated and real versions of an integrated circuit (IC) includes an IC simulator, a simulator manager, an IC tester, and a tester manager. The IC simulator simulates response of the IC to a set of simulated IC input signals by producing a set of simulated IC output signals. The simulator manager, programmed by a user-supplied test bench file, provides the simulated IC input signals to the simulator during the simulation. During the simulation, the simulator manager also generates a set of waveform data sequences, each representing periodically sampled values of a corresponding one of the simulated IC input and output signals. The IC tester includes a separate channel corresponding to each real IC input and output signal. The tester manager converts the waveform data sequence corresponding to each simulated IC input and output signal to a separate set of instructions provided as input to a corresponding one of the IC tester channels.

Abstract: A circuit for inserting a parity signal into a data stream, including a precoder circuit to precode the data stream to be written on a medium by generating a precoded data stream; a parity circuit to generate a parity signal based on said data stream at a predetermined time; and an insertion circuit to insert said parity signal into said precoded data stream.

Abstract: A communications system for communicating a serial bit stream and parity is disclosed which enables the use of the parity bit for signaling between the transmitter and receiver by selectively inducing parity errors. The system includes a first parity generator used to generate a first parity bit on the data to be communicated. The first parity and the data are transmitted in a communications medium by a data transmitter to a data receiver. A second parity generator generates a second parity bit using the communicated data. A comparator then compares the first parity bit with the second parity bit and a parser parses the received data in response to the comparison.

Abstract: A Viterbi decoder is disclosed that utilizes minimum memory for the decoding operation. A plurality of FIFOs are provided which are divided into two blocks of FIFOS, one for upper states and one for lower states. The operations are calculated utilizing previously stored branch metrics and then determining the new branch metric by retrieving information from the FIFOs, adding the new branch metric defined with the soft decision table and then selecting the most likely path therefrom, and discarding the other. This new branch metric is then stored back into the FIFOs to replace the old. Each branch metric calculation results in a determination of the most likely path for that state and also the decoded data bit for a given state associated with a received symbol. This is stored in a separate memory for each of the nodes, and thereafter, the output is decoded to retrieve the decoded bit stream.

Abstract: An error correcting and detecting apparatus for a CD-ROM or DVD system executes a high speed decode process. The apparatus includes an input interface, a temporary memory, a correcting circuit, a detecting circuit, a principal memory, and an output interface. The input interface fetches digital data in a block by block manner. The temporary memory stores the fetched digital data in a block by block manner. The correcting circuit performs error correction on digital data read from the temporary memory in a block by block manner using the error correction code and rewrites erroneous digital data to the temporary memory with the corrected digital data. The detecting circuit performs error detection on the error corrected digital data and supplied from the temporary memory in a block by block manner using the error detection code and sets an error flag based on a detection result.

Abstract: An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.

Abstract: A method for testing sequential circuit designs in which an exhaustive sequence of test vectors is applied to the input nodes of edge-sensitive components of a simulated sequential circuit. The test vector values are selected from a group including a logic “1” (high), a logic “0” (low), a “floating” value (i.e., between logic “1” and logic “0”) and a randomly generated (“don't care”) value. While a predetermined combination of values is applied to all other input nodes of the simulated circuit, the sequence of test vector values is applied to a selected input node that produces all possible transitions between the test vector values. The predetermined combination of values applied to all other input nodes is then incrementally changed, and the test vector value sequence is repeated.

Abstract: A technique for a scan design employing a register transfer level scan selection which requires that either all bits of a register are designated to have all scan or all non-scan properties. No separate elements (bits) of a register are selected for individual scan. By designating scan selection at the register level, register-transfer-level (RTL) specifications of a digital circuit can employ signal flow vectors at the register level and not at the conventional logic gate level. In one technique, a number of registers are grouped to have the same scan or non-scan property. Such grouping is used to provide a common template for inserting scan into multiple instantiated modules. The group designation for selecting scan or non-scan registers is also used to scan registers at the memory input, output, both input and output, or neither, which then can be used for testing memory devices.

Abstract: To offer a Reed-Solomon decoding device that can effectively prevent erroneous correction. A Reed-Solomon decoding method that conducts error correction and decodes by using erasure positions showing the position of units of errors for a Reed-Solomon encoded string having parity data of 2t (positive integer) units, which finds the number n for the unit of the error from the above-mentioned erasure position (S13), in the event 0 ≦m1≦n≦m2≦2t (m1, m2, and n are positive integers) (S14, S15, S18), finds the error value by conducting decoding calculations for the erasure error correction of n units (S19), and conducts the error operation by using the above-mentioned error value and the above-mentioned erasure position (S17).

Abstract: A system for coupling a Dynamic Termination Logic (DTL) type output driver to IEEE 1149.1 boundary-scan circuitry includes a logic circuit that converts the data and output enable signals of the IEEE 1149.1 specification to test “q_up,” “q_dn” and “q25_dn” signals meeting the requirements of the DTL driver. These test q_up, q_dn and q25_dn are selectively provided to the DTL driver during boundary-scan testing of the output driver. In a further refinement, the system also converts functional q_up, q_dn and q25_dn signals provided by the circuit under test to the data and output enable signals of the IEEE 1149.1 specification. The system allows the widely used IEEE 1149.1 boundary-scan standard to be used with DTL drivers. The resulting compatibility simplifies the testing and use of the DTL drivers, and provides a new boundary-scan standard for use with DTL drivers that is compliant with the IEEE 1149.1 standard.

Abstract: An antenna compensation system and method equalizes transmission link efficiency in sectors having unequal antenna or path gain while maintaining an equalized power spectral density. Areas of a sector having lower gains receive broadcasts with more robust coding to equalize their transmission link performance with areas of a sector having higher gains. The robustness of coding is controlled through setting of different forward error code rates, setting of different modulation types, or a combination of both. In analog systems it is controlled through variation of a signal-to-noise sensitive transmission parameter. Sectors may be divided azimuthally with areas at or near the boresight receiving less robust coding and areas nearer the sector edges receiving more robust coding. Similarly, sectors may be divided into radial areas with the more distant areas receiving more robust coding.

Abstract: A system and method identifies Iddq test vectors to be used in IDDQ testing of large CMOS circuits. This is achieved through intelligent preprocessing techniques. By monitoring only those nodes in the circuit that may be responsible for leakage current in the steady state, the size of the simulation results file is drastically reduced. The reduced simulation results file makes simulation a viable solution for IDDQ vector identification.

Abstract: In a semiconductor integrated circuit, a select signal output circuit switches a selector to take in the output of a circuit section in response to a signal “0” received at the D terminal thereof during normal operation. Thus, a scan flip-flop receives the output of the circuit section. During a scan test mode, a select signal “0” or “1” is input through a scan-in terminal to the select signal output circuit and then to the selector. If the select signal is “0”, then the selector selects the output of the circuit section. On the other hand, if the select signal is “1”, then the selector selects a clock signal supplied from a clock signal generator. The output of the circuit section or the clock signal supplied from the clock signal generator, which has been input to the scan flip-flop, is passed through a scan path and output to the outside through a scan-out terminal.

Abstract: An integrated circuit tester includes a host computer, a pattern generator and a set of tester circuits for performing a series of tests on an integrated circuit. The pattern generator is programmed to supply a sequence of pattern data as input to the tester circuits for controlling their operations during each test of the series. The pattern generator may also be programmed to interrupt the host computer before or during any test whenever it is necessary for the host computer to carry out an activity. The host computer may be programmed to respond to an interrupt by writing parameter control data into the tester circuits to reconfigure their operating characteristics, by acquiring test results from the tester circuits, or by directly controlling tester circuit operations during a test. When necessary to provide sufficient time for the host computer to carry out its task, the pattern generator may be programmed to temporarily suspend supplying pattern data to the tester circuits after sending an interrupt.

Abstract: A Java-based method for performing Boundary-Scan Test procedures on an IEEE Standard 1149.1 compliant integrated circuit device. A Boundary-Scan Test application procedural interface (BST API) is provided that includes several objects defining the Boundary-Scan architecture of IEEE Standard 1149.1 compliant integrated circuit devices, and defines a plurality of Java-based source code commands utilized in applets for performing Boundary-Scan Test procedures. To facilitate implementing a single applet on a wide variety of hardware platforms, the BST API is based on a command structure subset implemented by a wide range of available Java flavors.

Abstract: First and second digital data to which a code to correct errors was added are inputted. For a certain period of time, processes to detect errors in the first and second digital data are executed in accordance with the order of the first digital data and the second digital data. In this period of time, on the basis of the processing results, processes to correct the errors in the first and second digital data are executed in accordance with the order of the second digital data and the first digital data. Thus, the error detecting processes of the digital data that is inputted on a predetermined unit basis can be executed in parallel and an error correcting process in which a circuit scale is small and costs are low can be realized.

Abstract: The scan flip-flop that controls a bi-directional or a switchable high-impedance driver is implemented so that, when a logic value on a first input is latched in response to a first clock signal, and a logic value on a second input is latched in response to a second clock signal, both logic values are output during the second clock period.