Abstract: A Dynamic Random Access Memory (DRAM) configurable by eight (.times.8) or by nine (.times.9). The DRAM has nine Data Input/Outputs (I/Os). The memory array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is configured .times.8, one I/O is held in its high impedance state; one ninth of the DRAM's data path (between the array and the ninth I/O) is ignored; and, the entire array address space is available for data storage through eight I/Os. When the DRAM is configured .times.9, all nine I/Os are active; the DRAM I/O path is reconfigured with part of the array providing the ninth bit through the ninth I/O; and the array address space reduced by one-eighth. All nine bits may be from a common sub-array. Alternatively, sub-arrays may be paired so that when the DRAM is configured .times.9, eight bits are accessed in seven-eighths of one sub-array, with the ninth bit being accessed in one eighth of the other sub-array of the pair.

Abstract: Given a target frequency (F.sub.VE), a reference frequency (F.sub.R), an error limit (E.sub.L), and a first divider range (150), a first (R) and a second (N) integer divider value are computed. First, an initial first divider (R) is selected (152). Then, a second divider (N) is computed as equal to the target frequency (F.sub.VE) divided by the reference frequency (F.sub.R) multiplied times the selected first divider (154). Then an error term (E) is computed to quantify the error introduced by using integers as dividers (156). The divider terms are accepted (166) if the error term is less than the error limit (158). Otherwise, a new first integer divider (R) is selected (160), repeating the computation of the second (N) divider (154), the computation of the error (E) term (156), and the test of the error term (E) against a limit as a loop (158). This loop is repeated until either the error term (E) is less than the error (E.sub.

Abstract: A low-overhead scheme for built-in self-test of digital designs incorporating scan allows for complete (100%) fault coverage without modifying the function logic and without degrading system performance (beyond using scan). By altering a pseudo-random bit sequence with bit-fixing logic at an LFSR's serial output, deterministic test cubes that detect random pattern-resistant faults are generated. A procedure for synthesizing the bit-fixing logic allows for complete fault coverage with low hardware overhead. Also, the present approach permits the use of small LFSR's for generating the pseudo-random bit sequence. The faults that are not detected because of linear dependencies in the LFSR can be detected by generating more deterministic cubes at the expense of additional bit-fixing logic.

Abstract: An electronic integrated circuit includes a signal path connected between the functional logic thereof and an external output terminal thereof which signal path includes a memory circuit. The memory circuit is coupled to the output terminal and is selectively operable to detect and resolve voltage contention at the output terminal, and is also selectively operable to isolate itself from voltages at the output terminal.

Abstract: A connection matrix for a microcontroller emulation chip, which comprises memory cells of the RAM type comprising: first and second MOS transistors connected in series with each other between first and second voltage references, and having their drain terminals in common to form a first internal circuit node; third and fourth MOS transistors, also connected in series with each other between the first and second voltage references, and having their drain terminals in common to form a second internal circuit node; wherein the first and second transistors have their control terminals connected together and to the second internal circuit node, and the third and fourth transistors have their control terminals connected together and to the first internal circuit node; and fifth and sixth MOS transistors, respectively connected between first and second input terminals of the RAM cell and the first and second internal circuit nodes, and having respective control terminals connected to a third input terminal of the RA

Abstract: A test point analyzing apparatus determines a distinction between capability and incapability of insertion of a test point and a circuit modifying way when a test point is capable of being inserted for each of the test point types to each of the signal lines in a semiconductor integrated circuit by using circuit information, a test point insertion library, and test point insertion. Then, test point indexes to test point candidates capable of being inserted are calculated, and test point candidates having a large testability are selected based on the indexes, and the selected test point candidates are registered in test point information. Such processing is repeated until a predetermined condition of completing the test point analysis process is realized.

Abstract: The invention relates to a test circuit and a test system which provides interconnect test capability for modules and boards. The test circuit comprises a plurality of scan chains, including a plurality of registers. The registers in each module or board are logically sorted such that identical registers are arranged successively.

Abstract: An add/compare/select (ACS) processor in a Viterbi decoder is disclosed.