Abstract: According to the principles of this invention, a disk drive includes a page mode buffer memory controller that is used to control transfer of data from and to a buffer memory. The page mode buffer memory controller transfers a page of Nb data bytes from the buffer memory to a host of the disk drive if the data transfer is not interrupted by another request to the page mode buffer memory controller. The transfer of Nb data bytes requires only four overhead clock cycles. The page mode buffer memory controller includes a buffer prioritizer, a memory sequencer, a disk FIFO circuit, a refresh counter, a buffer address generator, and a disk byte counter. The buffer prioritizer receives request signals on port input lines and generates control output signals to the memory sequencer, disk byte counter and buffer address generator. The refresh counter repetitively loads itself with a refresh time period, that is stored in a register, for refreshing the buffer memory.

Abstract: A bus cycle timing control circuit that includes a timing control circuit that responds to a data request form a CPU and generates various read/write control signals for the purpose of controlling a bus cycle, a latch for storing a numerical value N, a register for holding a constant number "0", and a counter that starts counting down from the numerical value N held in the latch in response to the completion of one read/write control control signal. The timing control circuit includes a bus cycle start enable/disable circuit for generating a bus cycle start enable/disable signal which inhibits the start of a next bus cycle until the count value of the counter reaches the number "0" and which permits the start of the next bus cycle when the count value of the counter reaches the number "0".

Abstract: A host interface for a logic simulation machine for transferring data between the logic simulation machine and a host computer is disclosed. The host interface includes a First-In First-Out buffer provided between the logic simulation machine and the host computer for temporarily storing data being transferred between the logic simulation machine and the host computer until a receiver of the data is ready to receive the data. The host interface minimizes delays due to host interaction with the logic simulation machine during the communication between the host and the logic simulation machine.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: A token ring concentrator port circuit including an upstream data node, a downstream data node, a station receiver node, a station transmitter node, a path switch configured to selectively either connect the upstream data node directly to the downstream data node or connect the station receiver and transmitter nodes between the upstream and downstream data nodes, and a timing recovery circuit including a phase locked loop that derives a recovered clock from data from a station connected to the station receiver and transmitter nodes and reclocks the data with the recovered clock before transmitting the data to the downstream data node, the phase locked loop including a constant gain phase detector, the timing recovery circuit including a frequency limiting circuit, the port circuit components being implemented in a common integrated circuit.

Abstract: An archival and retrieval system which is connected to a host computer through an asynchronous serial line. The system operates unassisted through this serial line and appears like another terminal to the host. The system includes an archival and retrieval workstation containing archival and retrieval software for controlling the memory management operations. A portion of the archival and retrieval software resides in the host and contains archival and retrieval stacks for receiving and storing archive and retrieve requests respectively from user operated terminals. At periodic intervals the archival and retrieval workstation polls the archival and retrieval stacks to see if there are any requests present. If there are, the request is transferred to the workstation and used to either store or fetch the appropriate data item. The archival and retrieval workstation includes an archival storage media such as a optical disk.

Abstract: The system of controlling CPUs in a virtual computer system in which virtual computers are operated by assigning CPU resources to a plurality of virtual computers (guest VMs) according to optional ratios aims at effectively utilizing actual CPUs with predetermined assignment ratios duly maintained even if the CPU assignment ratios are unequally set among a plurality of guest VMs.

Abstract: A soundless period is detected from audio data stored in a memory medium, and soundless portion data relevant to the detected soundless period is eliminated. Sound portion data following the soundless portion data is stored right after previously stored sound portion data, so that audio data is compressed. When the audio data is reproduced, the soundless portion data is generated during the soundless period, and the original sound is reproduced. Soundless portion data is inserted into an arbitrary portion of the audio data to form a break. This soundless portion data is not stored in the memory medium, but, in a playing mode, the soundless portion data is automatically generated from a designated time for a designated period.

Abstract: A disk drive array with a controller which provides: dynamic remapping for grown defects in the disk drives, multi-thread request processing with a variable number of forkings, defect tracking with both logical and physical lists, guarded writes of less than a full stripe optimized by selectably using the redundancy to limit the number of sectors involved, association of multiple operations with a single disk request in order to facilitate error handling, use of an access hiatus as indication of further opportunity to rebuild data in background, and scatter/scatter (bidirectional scatter/gather) operations.

Abstract: An interface provides a path to transfer data from a proprietary network to an open system. The proprietary network includes at least one module central processing unit (CPU) and a module memory associated therewith operatively connected to the proprietary network. A shared memory and shared memory logic are interposed between the proprietary network and the open system, thereby forming the data path. The method comprises the steps of accepting requests for data from the open system by a parasitic task function within the module CPU. The data requested of the proprietary network is obtained and placed in a predetermined location of the module memory in a form understandable to the open systems. A pointer value is placed in the shared memory, the pointer value containing the value of the predetermined location of the module memory, the shared memory being mapped in the addressable memory space of the shared memory logic using virtual memory techniques.

Abstract: A computer system comprising a CPU and a scheduler. The CPU sets a predetermined value in the status variable corresponding to a thread when the thread starts waiting for a resource which it shares with other threads. The scheduler refers to the status variable, selects, with priority, a thread other than the thread waiting for the shared resource, and allocates the CPU to the thread thus selected.

Abstract: A data communication method between a master system and multiple slave systems using a serial input/output interface. The master system connects a communication path to a corresponding slave system, and transmits a message and simultaneously receives a message from the slave system during an assigned communication time. When the transmission of the message ends, the master system transmits a final message and when a final acknowledgement message is received, performs a service for the next slave system. Meanwhile, the slave system receives a message transmitted by the connection of the communication path and simultaneously transmits a message to the master system. Further, when a final message is received, the slave system transmits a final acknowledgement message to the master system. Thus, the effective communication between point-to-multipoint can be achieved.

Abstract: A data processing apparatus includes a first (k.times.m)-bit data bus wherein k is a byte count and m is a bit length of one byte, a plurality of m-bit I/O peripheral devices at least one which is connected to two or more of m-bit data buses belonging to a first group consisting of first to k-th m-bit data buses obtained by dividing the first (k.times.m)-bit data bus into the first to k-th m-bit data buses; a second (k.times.m)-bit data bus, a (k.times.m)-bit I/O central processing unit connected to the second (k.times.m)-bit data bus which is divided into (k+1)-th m-bit data buses consisting of a second group of m-bit data buses; a data path switching circuit connected between the first and second (k.times.m)-bit data buses which forms a data transmission path between an arbitrary two of said plurality of m-bit I/O peripheral devices and the CPU, and a transmission control circuit for generating control signals responsive to a demand of data transmission from said CPU.

Abstract: An on-line data processing system for providing a traffic control over the message queuing buffers that temporarily store the messages in order to absorb the difference in the message processing speed between the on-line program processing unit and the transmission/reception unit connected to a plurality of terminals. The traffic control is provided such that the message is stored or obtained in or from the message queuing buffer in accordance with the priority set on the messages. The priority of the messages is determined by using a character string in a predetermined position in each message.

Abstract: A data transfer control apparatus for communicating data between a host device and an input/output device through a main buffer memory for temporarily holding the data, wherein a sub-buffer memory is disposed at least either between the main buffer memory and the host device or between the main buffer memory and the input/output device for temporarily storing the data, the amount of data stored in the sub-buffer memory is detected, access requests to the main buffer memory on the side of the host device or the input/output device are outputted in accordance with the detected data amount, and one of the access requests to the main buffer memory is selected in accordance with the priority order to access the main buffer memory on the basis of the selected access request.

Abstract: A method and system for establishing multiple parallel conversations between a single pair of instances corresponding to a pair of communicating transaction programs over a data communication network. Each conversation traverses the network between the two communicating transaction program instances over a corresponding logical unit-logical unit session. Each conversation may be independently disconnected or reconnected without the need for invoking additional instances of the communicating transaction programs.

Abstract: To enable data transfer between desired clock synchronous serial input/output devices without the need of a specific transmission/reception protocol, ordinary data and device number data for specifying a receiving input/output device are transmitted as data to be transmitted. When the data to be transmitted is the device number data stored in an identification information register, an input/output device having this device number is selected, and data is transferred to the input/output device.

Abstract: For a virtual connection set up using an asynchronous transmission method which transmits information cells with a rate which is not constant over a relatively long period, the maximum rate may be limited, on the one hand, and the access of the information cells to a trunk line carrying information cells of a plurality of virtual connections may be regulated, on the other hand. As a result, the rate of information cells of a virtual connection is limited.

Abstract: A programmable logic controller is provided in which I/O modules situated in respective slots are coupled to a CPU by a main bus including a serial data line. A dedicated slot enable line is provided from the CPU interrupt controller to each slot into which an I/O module may be positioned. In this manner, the CPU can enable a selected I/O module when desired. The I/O module includes an interrupt feature wherein an interrupt signal is provided to the same slot enable line which communicates a slot enable signal to the I/O module. The I/O module returns an interrupt on the slot enable line at times other than when the slot enable line is being used by the CPU interrupt controller to send a slot enable signal. The CPU interrupt controller includes an interrupt detection circuit which makes a determination of when two conditions simultaneously occur, namely when both a particular slot enable line is active and the CPU is not enabling the corresponding slot with the slot enable signal.

Abstract: A hierarchical network hierarchically connects a plurality of networks whose nodes are mutually connected by connection paths as a p-array n-dimensional cube to configure a single network. A plurality of nodes are selected from lower layer p-array n-dimensional cubes, and the selected gate nodes are mutually connected as a p-array m-dimensional cube to configure a p-array m-dimensional network on the next layer. Similarly, gate nodes are selected from a plurality of next-layer p-array m-dimensional networks, and mutually connected as a p-array l-dimensional cube to configure a p-array l-dimensional network in a further upper layer, thereby configuring a single hierarchical network as a whole.