Abstract: A programmable disk array controller distributes contiguous data from a host processor across a plurality of disk drives. The controller includes a device port with a plurality of connected disk drives. A dual ported buffer memory receives data from the host processor for storage to the disk drives. The programmable controller accesses data from the buffer memory and causes it to be fed to the device port for storage in the disk drives. The programmable controller includes a variable increment counter associated with each disk drive for controlling the data address accessed from the buffer memory. Each variable increment counter is programmable to sequentially increment a count by a value n so that its associated disk drive receives every nth data segment from the buffer memory.

Abstract: A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycle to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer buffer RAM.

Abstract: Systems allowing smooth, trouble-free, "transparent" switchover from a "Primary clock" to a "Secondary clock", with no loss of clock or essential pulse-width, and where the "Secondary clock" may be completely separate from, and independent of, the "Primary clock.

Abstract: A computer bus that enables bus mastering agents to send/receive a burst of data to/from a slave agent without determining in advance the number of data words to be transferred, or even the maximum number of data words that could be transferred. Either the master, the slave, or the bus arbiter can terminate the burst at any time with minimum overhead. Furthermore, either the master or the slave can throttle the speed of the data transfer by adding wait states. Distributed address decode is performed by each agent coupled to the bus. Each agent must claim a transaction directed toward it by the master. If no agent claims the transaction within a predetermined number of clock periods, a subtractive decode device may claim the transaction by default. The bus also includes a bus lock wherein each bus slave agent may be able to enter a locked state, and once in the locked state, reject all accesses except those initiated by the master agent that locked it.

Abstract: A message path mechanism in a network having central processing complexes (CPCs) joined by message paths to a coupling facility. The coupling facility locates message paths for sending messages from one CPC to another and for sending messages between the coupling facility and one or more of the CPCs. A message path status table is provided having an entry for each of the message paths. Each entry has an indicator indicating whether its message path is active or inactive. multiple connections between the coupling facility and systems in the CPCs are registered in the coupling facility. Also provided is a mechanism for validating that each message path is connected properly such that if a message path is disconnected and then reconnected to a CPC, the validation mechanism insures that the message path has been reconnected correctly.

Abstract: Installation comprising several receiving points and several transmitting points. A control installation especially useful for controlling the operation of roller blinds or shutters. The control installation has several receiving points (4), several transmitting points (1) and the relay points (2) are connected to a common BUS line so as to be able to intercommunicate. The transmitting points (1) are provided in order to transmit signals on the BUS line. Each signal is a frame formed of at least one identifying element and of at least one element defining an order to be executed by the receiver. A particular address code, to which the identifying element corresponds is assigned to each transmitting point. The relay points are equipped with a logic processing unit having memories which are provided in order to store at least one identifying element. The allocating of the address to the transmitter allows the control installation to exhibit very high flexibility.

Abstract: A cost-effective motion control system communication architecture is provided that supports a centralized control node, distributed control nodes, and smart I/O peripheral control nodes. Networks designed using this architecture, which employs a serial bus, may be readily modified or expanded. The architecture supports both real-time highly periodic communications and event-driven peer-to-peer communications.

Abstract: A circuit device for interconnecting several processing units equipped with microprocessors includes at least two connection ports connecting the circuit device to the processing units, including a control unit for managing connection peculiarities using lock intelligence; an interface control unit for interfacing the processing units to memory; control unit for controlling the circuit device, connected to the connection ports and to the interface control unit, and for handling reading and writing of data to and from the connection ports and the interface control unit.

Abstract: A method and system for controlling access to a system bus in a computer system is provided. The system devices include a central processing unit, a memory controller for controlling access to system memory, and at least one input/output device having a coprocessor incorporated therein. The system bus electrically connects the system devices. Any one of the system devices may serve as a bus master of the system bus at any one time when communicating over the bus with each other or with system memory. Each of the at least one input/output device incorporates control logic therein for (i) monitoring bus activity to calculate the bus mastering time during which the memory controller and the at least one input/output device control the bus, and (ii) outputting an inhibit signal which denies access to the bus by the at least one input/output device if the calculated bus mastering time is equal to or greater than a predetermined bus mastering time period.

Abstract: A network video server apparatus and method for transferring video image data across a computer network serving multiple clients. The network server apparatus comprises two parts, a server and a client. The server is run on a computer system containing a video digitizer hardware. Running the server on this computer system makes it possible to distribute video images across an existing network linking several client computer systems. The client provides the user with a means of viewing the images generated by the server through the network, controlling the size and type of image to be sent by the server, controlling the underlying video digitizer hardware, and collecting statistics about the server/client performance. The client software is designed to appear to the users as if they were operating the client software locally. The server and client communicate with each other over two channels: one for control information and another for video data.

Abstract: A system for direct interprocessor communication in a multiprocessor data processing environment. The system utilizes conventional direct data transfer means and existing I/O port instruction capabilities available on most microprocessors. A destination processor requiring data from one of a source processor's internal registers generates a unique address which specifies the register containing the required data. The address is sent to the data transfer means, causing the direct transfer of data from the designated source processor internal register to the destination processor. Specific circuitry to accomplish this direct data transfer function is described.

Abstract: A high speed data communication controller comprising two independent central processing units, each having its own independent program instruction fetch data path, and instruction execution data path. The data communication controller includes a dual-port serial communication subsystem and a bus interface unit operably associated with a four channel DMA controller. One central processing unit is assigned the task of handling the medium access control (MAC) layer function of a multilayered local area network protocol, while the other central processing unit handles host commands and buffer memory management functions associated with the transmission and reception of packets relating to the higher layer protocol. As a result of the present invention, efficient data communication processing is achieved within a single VSLI chip, thereby improving node and network data throughout.

Abstract: In a situation where a first computer program has been translated to obtain a second computer program, an error occurring during execution of the second computer program is reported in the context of the first program. This is done by aborting execution of the second computer program when the error occurs; determining a first address which is the address of the instruction in the second computer program that caused the error; determining from the first address a second address of an instruction in the first computer program from which the instruction in the second computer program was translated; and reporting that the error occurred, and using the second address to indicate that the error is associated with the instruction in the first computer program. Preferably the second address is used to reference traceback and symbolic name information generated when the first computer program is compiled from source code.

Abstract: A communication processing system provided with one parent communication unit, at least one child communication unit, and at least one first detachable unit detachable from the at least one child unit, the system being operated in accordance with an operation program stored in a second detachable unit detachable from the parent unit, includes a transfer unit for transferring the operation program to the at least one child unit, a first storage unit for storing the operation program transferred from the parent unit by the transfer unit when the second detachable unit is mounted on the parent unit, the first storage unit being provided in the first detachable unit, and a second storage unit for storing a receiving program for receiving data sent from the parent unit, the second storage unit being provided in the first detachable unit. The first storage unit is provided in the first detachable unit. The second storage unit is provided in the first detachable unit.

Abstract: Apparatus for switching data to a bus including apparatus for driving a bus to a first data receiving condition during a first clock period, apparatus for driving the bus to a second data awaiting condition during a second clock period, apparatus for releasing the bus from the second data awaiting condition during the second clock period, and apparatus for maintaining the bus in the second data awaiting condition.

Abstract: In a data processing system having a central processing unit including a register file for storage of often-used data, a method and system is provided for saving and restoring the contents of the register file from the main memory only when necessary. Each register unit in the register file includes a register protection flag, a save area pointer and a plurality of general purpose registers. The register protection flag is coded to identify if the register unit is in actual use by having contents stored in any of the general purpose registers. Before saving or restoring the register unit, its register protection flag is checked, and only if the flag indicates actual use is the saving or restoring performed.

Abstract: This invention relates to electronic equipment comprising microprocessors, and more specifically microprocessors employed within radio receiver circuits, incorporating on-chip memory (301, 302, 303) and which have the ability to operate in either a single chip or expanded mode. The single chip mode restricts microprocessor (300) operation to internal operation and thereby inhibits external addressing and locally generated noise whereas the expanded mode allows external addressing. A software program, comprised from modules of program code, is categorised into a first and a second category of routines. First category routines are related to equipment functions which are affected by generated noise to a higher degree and, when in operation, are stored in the internal memory (301, 302, 303). Second category routines are stored in a memory external to the microprocessor (201, 202) and are related to equipment functions which are affected by generated noise to a lesser degree.

Abstract: In a communication system having a plurality of host computers and two communication control processors (CCPs) connected to the respective host computers, one CCP is used as a regular CCP and the other CCP as a backup CCP. Each host computer establishes links with the two CCPs. Each of the host computers has a link flag for each link connected to each of the CCPs. The flag is set when the link is connected to the regular CCP. When the master host computer detects failure of the regular CCP, the master host computer sends an activate node request to the backup CCP to indicate that the backup CCP should be activated. Upon reception of the activate node request, the backup CCP sends a change output link request to all of the host computers. Upon reception of the change output link request, each of the host computers sets the link flag corresponding to the backup CCP to deal with the backup CCP as a regular CCP.

Abstract: A cost-effective motion control system communication architecture is provided that supports a centralized control node, distributed control nodes, and smart I/O peripheral control nodes. Networks designed using this architecture, which employs a serial bus, may be readily modified or expanded. The architecture supports both real-time highly periodic communications and event-driven peer-to-peer communications.

Abstract: Four clusters of 16 CPU's each are each associated with a solid state memory and a main memory. Each CPU is uniquely associated with a channel arbitrator which interconnects the associated CPU to serial ports. Each channel arbitrator is associated with a set of 16 serial channels. Each serial channel is in turn interconnected to a channel adapter which includes software and firmware adapted for interacting with a specific peripheral device. Each channel adapter also has software and firmware which is device-independent for data transfer with the channel arbitrator. The channel arbitrator includes a memory port for accessing main memory through the CPU, a port for accepting service requests and providing interrupts to the CPU's, direct memory access control logic, arbitration control logic, serial ports associated with the channel adapters, and a parallel port is associated with solid state memory.