Abstract: A memory controller includes, in one embodiment, a memory interface, a plurality of decoders, and a controller circuit. The memory interface is configured to interface with a memory having a plurality of wordlines. Each decoder of the plurality of decoders is configured to determine a bit error rate (BER). The controller circuit configured to generate a plurality of bit-error-rate estimation scan (BES) hypotheses for one wordline of the plurality of wordlines, divide the plurality of BES hypotheses among the plurality of decoders, receive BER results from the plurality of decoders based on the plurality of BES hypotheses, and adjust one or more read locations of the one wordline based on the BER results from the plurality of decoders.

Abstract: A semiconductor device comprises a plurality of memory elements, test control circuitry, and a testing interface. The test control circuitry is configure to determine that one or more clock signals associated with the memory elements have been stopped and generate a scan clock signal based on the determination that the one or more clock signals have been stopped. The test control circuitry is further configured to communicate the scan clock signal to the memory elements. The testing interface is configured to communicate test data from the memory elements. In one example, the test data is delimited with start and end marker elements. The semiconductor device is mounted to a circuit board and is communicatively coupled to communication pins of the circuit board.

Abstract: A method for detecting error on an input/output (IO) pin of an integrated circuit includes using the input/output pin of the integrated circuit in a first mode by receiving or sending a first value as analog data or digital data. The input/output pin is toggled in a test mode after each instance of using the input/output pin in the first mode. The test mode includes providing a second value disparate from the first value during a set time after using the input/output pin in the first mode, receiving back during the set time a resulting value based on providing the second value, measuring the resulting value, and identifying an error on the input/output pin of the integrated circuit based on the measured resulting value.

Abstract: The present technology relates to a transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. LDPC coding for information bits with an information length K=N×r is performed on the basis of an extended parity check matrix having rows and columns extended by a predetermined puncture length L with respect to a parity check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 14/16, so that an extended LDPC code having parity bits with a parity length M=N+L?K is generated. A head of the information bits of the extended LDPC code is punctured by L, so that a punctured LDPC code with the code length N of 69120 bits and the coding rate r is generated.

Abstract: A communications device receive data from a wireless communications network by detecting from one or more control channels of a wireless access interface one or more encoded data units of a plurality of encoded data units into which an error correction encoded control information has been divided in accordance with an incremental redundancy scheme. The communications device decodes the error correction encoded control information by combining the one or more detected encoded data units in accordance with an arrangement of encoded bits of the error correction encoded control information in each of the plurality of encoded data units. Each of the plurality of encoded data units comprises a different set of the encoded bits according to a different redundancy version number of the incremental redundancy scheme.

Abstract: Testability of memory on integrated circuits is improved by connecting storage elements like latches in memory to scan chains and configuring memory for scan dump. The use of latches and similar compact storage elements to form scannable memory can extend the testability of high-density memory circuits on complex integrated circuits operable at high clock speeds. A scannable memory architecture includes an input buffer with active low buffer latches, and an array of active high storage latches, operated in coordination to enable incorporation of the memory into scan chains for ATPG/TT and scan dump testing modes.

Abstract: Testability of memory on integrated circuits is improved by connecting storage elements like latches in memory to scan chains and configuring memory for scan dump. The use of latches and similar compact storage elements to form scannable memory can extend the testability of high-density memory circuits on complex integrated circuits operable at high clock speeds. A scannable memory architecture includes an input buffer with active low buffer latches, and an array of active high storage latches, operated in coordination to enable incorporation of the memory into scan chains for ATPG/TT and scan dump testing modes.

Abstract: An example memory device includes an array of memory cells, a plurality of boundary cells, mixed pads connected to the memory cells, high speed pads connected to the boundary cells, a three state multiplexer block connected to the memory cells and to the boundary cells and configured to receive at least first and second input signals, and the three state multiplexer block is connected to the mixed pads. The example memory device further includes an enabling circuit connected to a mixed pad and configured to receive an external enabling signal and provide the three state MUX with an internal enabling signal, and comprising: a tester presence detector circuit connected to the mixed pad and configured to provide a presence signal to a logical gate, the logical gate having input terminals connected to the tester presence detector circuit and configured to provide the internal enabling signal.

Abstract: A semiconductor device includes a selection input circuit and a core data generation circuit. The selection input circuit is configured to generate selection data, a selection parity, and a selection data control signal from data, a parity, and a data control signal during a write operation and sets the selection data, the selection parity, and the selection data control signal to a predetermined logic level during a pattern write operation. The core data generation circuit is configured to receive drive data, a drive parity, and a drive data control signal driven by the selection data, the selection parity, and the selection data control signal to generate core data which are stored into a memory core according to whether an error correction operation and a data inversion operation is performed.

Abstract: An apparatus and method for detecting leakage current in a non-volatile memory array. A reference current is connected to a leakage detection circuit. A reference code is determined for the leakage detection circuit coupled to a switching circuit. The reference code establishes a leakage current threshold. The reference current is disconnected from the leakage detection circuit and the switching circuit. Next, the leakage detection circuit is connected to a set of word lines of a storage block of a non-volatile memory array by way of the switching circuit. A memory current is generated within the set of word lines. A leakage code is determined for the set of word lines representing leakage current from the word lines in response to the memory current. The leakage code is compared with the reference code. If the leakage code exceeds the reference code, the storage block is deemed unusable.

Abstract: This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.

Abstract: A method of hierarchical structuring a multi-level memory in a convolutional neural network, includes partitioning a memory into a plurality of sections, partitioning the plurality of sections into a plurality of stripes, utilizing input data from the plurality of stripes in a MAC array, outputting an intermediate result from the MAC array to at least one of the plurality of stripes of a result buffer, looping back the intermediate result from the at least one of the plurality of stripes of the result buffer to at least one of the plurality of stripes of an input data buffer and outputting a final result from the at least one of the plurality of stripes of the result buffer to at least one of the plurality of stripes of an output buffer.

Abstract: The application provides a channel encoding method, an encoding apparatus, and a system. A bit sequence X1N is output by using X1N=D1NFN, where D1N is a bit sequence obtained after an input bit sequence u1N is encoded based on locations of K to-be-encoded information bits in an encoding diagram that has a mother code length of N, u1N is a bit sequence obtained based on the K to-be-encoded information bits, and FN is a Kronecker product of log2 N matrices F2. A design considers that the locations of the K to-be-encoded information bits in the encoding diagram that has a mother code length of N include a row location index set H of the information bits in the encoding diagram and a layer location index set M of the information bits in the encoding diagram, where 0?H?N, and 0<M?logm N?1.

Abstract: A method in a node (110, 115) comprises generating (604) a plurality of constituent polar codes, each of the plurality of constituent polar codes having an associated block length and an associated set of information bits. The method comprises coupling (608) at least a portion of the sets of information bits associated with each of the plurality of constituent polar codes to generate a spatially coupled polar code. The method comprises encoding (612) a wireless transmission using the spatially coupled polar code.

Abstract: A device includes a data path, a first interface connected to the data path and configured to receive a request from a processor package to write a data value to a memory address, and a controller connected to the data path and configured to receive the request to write the data value to the memory address and to calculate a Hamming code of the data value. The controller is configured to transmit the data value and the Hamming code on the data path. The device includes an external memory interleave connected to the data path. The external memory interleave is configured to receive the data value and calculate a test Hamming code of the data value and to determine whether to send the data value to an external memory interface to be written to the memory address based on a comparison of the Hamming code and the test Hamming code.

Abstract: Boundary test circuit, memory and boundary test method are provided. The boundary test circuit may include a plurality of serially-connected wrapper boundary registers (WBRs) and a plurality of toggle circuits (TCs). Each WBR may include a first I/O for receiving an initial test signal and a second I/O for transmitting the initial test signal to the WBR at a succeeding stage. Each TC may include an input for receiving the initial test signal stored in a corresponding WBR, a control I/O for receiving a toggle signal, and an output for transmitting a real-time test signal to the integrated circuit. The toggle signal may be configured to control phase switching of the real-time test signal, and, depending on the toggle signal, the real-time test signal may have a phase identical or inverse to a phase of the initial test signal. This method improves the efficiency and flexibility of the boundary test.

Abstract: The disclosed embodiments relate to method, apparatus and system for testing memory circuitry and diagnostic components designed to test the memory circuitry. The memory may be tested regularly using Memory Built-In Self-Test (MBIST) to detect memory failure. Error Correction Code (ECC)/Parity is implemented for SRAM/Register Files/ROM memory structures to protect against transient and permanent faults during runtime. ECC/Parity encoder and decoder logic detect failure on both data and address buses and are intended to catch soft error or structural fault in address decoding logic in SRAM Controller, where data may be read/written from/to different locations due to faults. ECC/parity logic on the memory structures are subject to failures. In certain exemplary embodiments, an array test controller is used to generate and transmit error vectors to thereby determine faulty diagnostic components. The test vectors may be generated randomly to test the diagnostic components during run-time for in-field testing.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode outer-encoded bits to generate an LDPC codeword including LDPC information bits and parity bits; a puncturer configured to puncture some of the parity bits included in the LDPC codeword; and a mapper configured to map the LDPC codeword except the punctured parity bits to symbols for transmission to a receiver, wherein the puncturer calculates a number of parity bits to be punctured among the parity bits included in the LDPC codeword based on a number of the outer-encoded bits, a number of the LDPC information bits, and a minimum number of parity bits to be punctured among the parity bits included in the LDPC codeword.

Abstract: One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

Abstract: The present invention provides a method, device, and system for testing devices under testing (DUTs). The method comprises: sending a scan activated signal and a synchronous clock signal via the second signal line, and sending a first preset signal via the serial signal line, wherein each bit of the first preset signal is transmitted to a corresponding scan chain unit in a sequence of serial connection of the plurality of scan chain units with according to the synchronous clock signal, the corresponding scan chain unit is one of the plurality of scan chain units connected serially and coupled to the plurality of DUTs via a third signal line; sending a scan deactivated signal via the second signal line, to deactivate the scan chain units from identifying and receiving the first preset signal; and sending a second preset signal via the second signal line, and sending a test signal via the first signal line.