Abstract: A receiver is arranged for receiving a signal comprising an interleaved symbol stream. The receiver comprises a convolutional deinterleaver comprising a plurality of delay portions each of which is arranged to delay symbols from the symbol stream from an input to an output by a different amount, the delay portions being arranged in a sequence. An input selector is configured to input the symbols from the symbol stream to the delay portions so that successive symbols are input in accordance with the sequence of the delay portions. An output selector configured to read the symbols from the delay portions by successively selecting the symbols from the outputs of the delay portions in accordance with the sequence of the delay portions to form a deinterleaved symbol stream.

Abstract: A program method of a nonvolatile memory device including a plurality of memory cells, each storing at least two bits of data, includes performing a first program operation based on a plurality of program voltages having a first pulse width to program first page data into selected memory cells connected to a selected word line among the plurality of memory cells; and performing a second program operation based on a plurality of program voltages having a second pulse width different from the first pulse width to program second page data into the selected memory cells in which the first page data is programmed.

Abstract: A testing device and a method for testing a device under test are provided. The testing device comprises at least two signal generators, at least two numerically controlled oscillators, at least two white gaussian noise generators, at least two digital filters, each of which comprising a respective transfer function Hi, at least two adders, at least two digital-to-analog converters, and an analog processor.

Abstract: A system comprises a testing mode register, a set of pins, and a test access port controller. The test access port controller initiates a first testing mode by configuring the set of pins according to a first pin protocol. The test access port controller configures a first pin to receive first test pattern data based on a first convention and configures a second pin to output first test result data based on the first test pattern data. Based on detecting a register command stored in the testing mode register, the test access port controller initiates a second testing mode by configuring the set of pins according to a second pin protocol. The test access port controller configures the first pin to receive a second test pattern data generated based on a second convention and configures the second pin to output a second test result data based on the second test pattern data.

Abstract: The present invention relates to data communication systems and methods thereof. More specifically, embodiments of the present invention provide a data transmission method. Data are encoded with staircase encoder, and staircase coded blocks are first interleaved then combined into outer code frames. Code frames additionally include sync words and padding bits. A second interleaving is applied to the bits of the code frames, and Hamming encoding is performed on the output of the second interleaver. Hamming codewords are Gray-mapped to dual-polarized quadrature-amplitude-modulation (DP-QAM) symbols, and a third interleaving of the symbols from a set of successive Hamming codewords is performed. Pilot symbols are inserted periodically into the stream of DP-QAM symbols. There are other embodiments as well.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver includes a block interleaver formed of a plurality of columns each comprising a plurality of rows, and the block interleaver is configured to divide the plurality of columns into at least two parts and interleave the LDPC codeword.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder which encodes input bits including outer encoded bits to generate an LDPC codeword including the input bits and parity bits to be transmitted to a receiver in a current frame; a puncturer which punctures a part of the parity bits which is not transmitted in the current frame; and an additional parity generator which selects at least a part of the parity bits to generate additional parity bits transmitted to the receiver in a previous frame of the current frame, wherein a number of the additional parity bits is determined based on a number of the outer encoded bits and a number of the parity bits left after the puncturing.

Abstract: The present technology relates to a data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 24/30, 25/30, 26/30, 27/30, 28/30, or 29/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The present technology may be applied to LDPC encoding and LDPC decoding.

Abstract: A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

Abstract: Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.

Abstract: A program method of a nonvolatile memory device including a plurality of memory cells, each storing at least two bits of data, includes performing a first program operation based on a plurality of program voltages having a first pulse width to program first page data into selected memory cells connected to a selected word line among the plurality of memory cells; and performing a second program operation based on a plurality of program voltages having a second pulse width different from the first pulse width to program second page data into the selected memory cells in which the first page data is programmed.

Abstract: This application relates to the field of wireless communications technologies, and discloses an encoding method and apparatus, to improve accuracy of reliability calculation and ordering for polarized channels. The method includes: obtaining a first sequence used to encode K to-be-encoded bits, where the first sequence includes sequence numbers of N polarized channels, the first sequence is same as a second sequence or a subset of the second sequence, the second sequence comprises sequence numbers of Nmax, polarized channels, and the second sequence is the sequence shown in Sequence Q11 or Table Q11, K is a positive integer, N is a positive integer power of 2, n is equal to or greater than 5, K?N, Nmax=1024; selecting sequence numbers of K polarized channels from the first sequence; and performing polar code encoding on K the to-be-encoded bits based on the selected sequence numbers of the K polarized channels.

Abstract: A method for compensating for a read error is disclosed, wherein each of n states are read from memory cells of a memory, the states being determined in a time domain. If the n states do not form a code word of a k-from-n code, a plurality of states from the n states, which were determined within a reading window, are provided with a first valid assignment and fed to an error processing stage. If the error processing does not indicate an error, the n states are further processed with the first valid assignment, and if the error processing indicates an error, the plurality of states that were determined within the reading window are provided with a second valid assignment and the n states are further processed with the second valid assignment. Accordingly, a device, a system and a computer program product are also disclosed.

Abstract: A DRAM device includes first terminals, second terminals, third terminals, a control signal generator, a CRC unit, a row decoder, a column decoder, and a memory cell array. The control signal generator generates a control signal. The CRC unit performs a first CRC logical operation on a first data group including qn-bit first data generated by inputting n-bit first data q times, generates a first CRC result signal, performs a second CRC logical operation on a second data group including qn-bit second data by inputting n-bit second q times, generates a second CRC result signal, and generates an error signal based on the first CRC result signal and the second CRC result signal. The error signal is generated based on the second CRC result signal regardless of the first CRC result signal in response to the control signal.

Abstract: A method includes generating an extended result from a first operation circuitry having a result register bit width greater than a bus width associated with a residue check path of a second operation circuitry associated with a floating point unit. An extended result residue less a first portion residue of the extended result received from the residue check path is stored as a first partial result residue. The first partial result residue is compared with a first result residue of the second operation circuitry. The extended result residue less both the first partial result residue and a second portion residue of the extended result received from the residue check path as a second partial result residue is compared with a second result residue of the second operation circuitry.

Abstract: A nonvolatile memory device performs a compare and write operation. The compare and write operation includes reading read data from memory cells, inverting first write data to generate second write data, adding a first flag bit to the first write data to generate third write data and adding a second flag bit to the second write data to generate fourth write data, performing a reinforcement operation on each of the third write data and the fourth write data to generate fifth write data and sixth write data, and comparing the read data with each of the fifth write data and the sixth write data and writing one of the fifth and sixth write data in the memory cells based on a result of the comparison.

Abstract: A method comprises: obtaining a coded bit sequence by performing PC-polar coding on information bits based on first constructor parameters; and sending the coded bit sequence. A check equation of the first constructor parameters includes a first element representing a check-required information bit position and a second element representing a check bit position, the first element corresponds to a first vector (V1) in a generator matrix for PC-polar codes, the second element corresponds to a second vector (V2) in the generator matrix, and if a first Hamming weight (HW1) of V1 is the same as a second Hamming weight (HW2) of V2, then a third Hamming weight (HW3) of an addition modulo 2 vector is greater than HW1 and greater than HW2, or if HW1 is different from HW2, then HW3 is greater than a smaller one of the HW1 and HW2.

Abstract: A memory dispatcher, including an address decoder configured to decode a write address of received write data; a lockstep processor configured to generate, based on the decoded write address, primary and redundant memory write addresses and corresponding primary and redundant copies of the write data, if the decoded write address corresponds with a lockstep region of the memory; and a comparator coupled to the lockstep processor, and configured to compare the primary and redundant copies of the write data, and to compare the primary and redundant memory write addresses.

Abstract: An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored as a currant value in a parity page of the parity buffer, the parity page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.