Abstract: An equivalent time sampler uses an oscillator for sampling an input waveform having a repetitive component. A periodic signal is derived from the input waveform, and an offset frequency is derived from the periodic signal. The periodic signal and offset frequency are input to an offset locked oscillator to generate a sampling frequency that is the combination of the periodic signal and the offset frequency. The sampling frequency is used to obtain a sample of the input waveform for each acquisition cycle of the waveform.

Abstract: According to this invention, a reference voltage generating circuit includes a first series circuit, a second series circuit, and a control circuit. The first series circuit is constituted by a first resistor, a first transistor, a second transistor, and the second resistor connected in series between power source terminals. The second series connection circuit is constituted by third and fourth transistors which have control electrodes respectively connected to a connection point between the first resistor and the first transistor and a connection point between the second resistor and the second transistor, are connected in series between the power source terminals, and have a common connection point serving as a reference voltage output terminal. The control circuit sequentially ON/OFF-controls the first and second transistors by a control signal.

Abstract: An improved direct digital frequency multiplier that multiplies input frequencies by a factor equal to the number of comparators in the circuit divided by two. The circuit includes a sensing stage, a ramping stage, a storage stage, a comparison stage and a logic stage. A signal containing the frequency to be multiplied is input to the sensing stage, which determines the frequency of the signal and outputs timing signals to the rest of the circuit. Coinciding with the period of the input signal, ramping voltages are generated, whose peak voltages are sampled and held for a specific time. The linearly ramping voltages are compared with the peak voltages and the comparison stage outputs voltage spikes to the logic stage. The logic stage combines the outputs from the comparison stage, and outputs a square wave signal possessing the appropriate multiplied frequency.

Abstract: A low-skew CMOS clock divider circuit for providing tracking of the divide-by-one and divide-by-two output signals obtained from a source of master clock pulses is fabricated using two matched flip-flops externally wired as divide-by-two devices. Coincidence gates are coupled with the outputs of the flip-flops to produce the desired divide-by-one and divide-by-two output signals in a manner such that the signals in each path pass through substantially identical circuit components, Thus, any delays encountered are the same in both circuit paths. In this manner, skew between the edges of the divide-by-two and divide-by-one clock signals is significantly reduced.

Abstract: A blocking architecture for use in non-volatile semiconductor memories is disclosed. This architecture minimizes device area taken up by signal lines while maximizing device yield. Additionally, this architecture minimizes the Y decoding mechanism while maximizing device performance.

Abstract: A digitalization assembly of the over-sampling type includes an analog to digital converter (2) producing at a frequency F=kf small-format p samples and a digital filter (3) which, through the summation of a certain number n of over-samples, produces validated larger P-format samples at the frequency f, at instants fixed by a clock. In order to readjust the sampling instants in relation to an outside event which can occur at any time, a temporary memory store (5) is inserted between the converter (2) and the filter (3) and, according to the instant of arrival of this event, the appropriate samples to be sent towards the filter for their summation are selected.

Abstract: A tuning circuit (10) and method of operation for tuning an analog filter (40). The tuning circuit (10) has an integrator with an input portion (12) and a comparator portion (14), a counter (32), and a decoder (34). The integrator is implemented with an RC time constant which is proportional to an RC time constant of the analog filter (40). The comparator portion (14) provides an enable signal during the RC time constant of the integrator to the counter (16) which quantizes the RC time constant relative to a clock period of the counter (16). A predetermined decoding is performed to provide an output control signal to control adjustment of the RC time constant of the analog filter (40).

Abstract: A clock stability circuit (10, 20, 30, 40) assures stable clock generator operation after oscillator start-up, such as during re-entry after a low-power Halt mode in a microprocessor or microcomputer. The clock stability circuit detects stable clock cycles that transition between a selected high amplitude threshold (near VDD) and a selected low amplitude threshold (near VSS), and provides a clock stable signal after a selected number of stable clock cycles, indicating that the oscillator has stabilized. The clock stability circuit includes four modules: input sampler (10), pulse generator (20), pulse counter (30) and control logic (40). The input sampler module includes CMOS NAND gates (11, 14) respectively fabricated with p/n-channel ratios to provide a CLOCK A signal that transitions at the selected high amplitude threshold of an oscillator cycle, and a CLOCK B signal that transitions at the selected low amplitude threshold.

Abstract: A high band weighting circuit of a noise reduction circuit is disclosed. For elevating a mid and high frequency component gain comparing with a low frequency component among input signal, the high band weighting circuit comprises a capacitor a dividing means a first voltage-to-current converting circuit, a second voltage-to-current converting circuit, a first current mirror circuit outputting a third current signal corresponding to a first current signal of the first voltage-to-current converting circuit, a second current mirror circuit coupling a fourth current signal to the output terminal corresponding to a second current signal of the second voltage-to-current converting circuit, and a third current mirror circuit coupling a fifth current signal to the output terminal corresponding to a third current signal of the first current mirror circuit.

Abstract: The specification discloses a magnetic recording signal reproducing apparatus for controlling a magnetic tape and reproducing magnetic heads.In the magnetic recording signal reproducing apparatus of the invention, a magnetic tape which is moved for magnetic heads attached to a rotary cylinder is traced by the magnetic heads and signals recorded on tracks of the magnetic tape are reproduced. A construction of the apparatus includes a tracking control system, a tape tension control system, and an apparatus for selectively switching operations of both of the control systems.

Abstract: In this invention, a plurality of clock buffers are provided to supply clock signals to a charge transfer apparatus. These clock buffers are driven by the same basic clock which is introduced through a plurality of clock logics. Accordingly, even if the charge transfer apparatus is comprised of a multi-stage charge coupled device having a large number of stages, those clock buffers still have enough ability to drive the charge transfer apparatus with high frequency. So, the driving circuit according to this invention can drive a multi-stage charge transfer apparatus with keeping the excellent frequency characteristics, even if the charge transfer apparatus is driven with high frequency.

Abstract: A programmable logic device is disclosed having a delay line macrocell with programmably selectable taps feeding inputs to a programmable logic circuit. The delay line taps may feed the programmable logic circuit through logic circuit driving circuitry, which performs a certain amount of prepossessing on the tap signals before being provided to the programmable logic circuit. Outputs of the programmable logic circuit, which may be a programmable AND array followed by a fixed OR array, are provided to the edge-triggered inputs of dual set/reset flip flops. Other outputs of the programmable logic circuit are selectable as inputs to the delay line.

Abstract: An N-bit binary counter includes N 1-bit counters together producing an N-bit binary word, and a count enable signal generator for generating count enable signals for each of the N 1-bit counters. The count enable signal generator includes multiple logic group/carry ripple devices, different ones of which receive different numbers of bits of the binary word and generate count enable signals for the same number of bits. The logic group/carry ripple devices also receive a carry ripple output signal from an adjacent logic group/carry ripple device and generate a carry ripple output signal for another adjacent logic group/carry ripple device.

Abstract: An automatic resident card dispensing system is provided in which in order to identify the user demanding the issue of a resident card, a question-and-answer session is held on the basis of the resident record data specific to the right user, and it is determined whether the user has entered correct answers to questions. When any of the answers is incorrect, the issue of the resident card is suspended. The system includes a resident record data base storing data items for issuing the resident card, a resident card dispensation processing section for issuing a resident card on the basis of the resident record data base, a display section for displaying questions and messages, an input section for entering answers to the questions displayed, and a user identification processing section for determining whether a right answer has been entered to each of the questions from the input section and suspending the issue of the resident card when any of the answers is incorrect.

Abstract: A method and an apparatus for synchronizing particle counts to process events provide a trigger signal related to the process events in lieu of a time-based trigger signal. In one embodiment, the controller to a particle counter further subdivides a process event into sub-intervals to allow profiling of particle counts during the process event. In one embodiment, the controller of the particle counter receives multiple trigger signals corresponding to multiple trigger signal sources, each trigger signal source being identified by a source tag. Particle counts and time-stamps are maintained for each source of the trigger signals.

Abstract: In an apparatus for controlling a moving speed of a magnetic head, servo data recorded beforehand on a recording medium is read out in sequence by the magnetic head while the magnetic head is moving. Position data indicative of the current position of the magnetic head is acquired on the basis of the read-out servo data and then a moving speed of the magnetic head is computed from the position data. When the remaining distance from the current position to the target track is less than a predetermined number of tracks, the speed of the magnetic head is so controlled that the rate of change in the target speed gradually decreases. The control gain is changed in accordance with the rate of change in the target speed.

Abstract: A circuit having a delay circuit provided with a gate for converting the output signal of an SR flip-flop into a signal with a delay equal to or more than the clock pulse width enough for count operation and leading the logical addition between the signal and system clock and the logical multiplication between the signal and counter write signal to the direct reset input of a transparent latch 7 and for realizing read-on-the-fly or write-on-the-fly operation even if timer input does not synchronize with the system clock.

Abstract: In discrete wafer-scale integration abbreviated as WSI, pre-tested chips are mounted and bonded on a pre-wired wafer. Silicon usually serves as the wafer substrate because the wafer wiring can be cost-beneficially produced with a standard multi-layer process. The conducting properties of such a wafer micro-wiring forbid the use of long leads given high timing clocks, so that intermediate drivers must be utilized. Previous solutions make use of separate driver chips that must be placed, bonded and tested in addition to the actual function chips. In the disclosed WSI system, the intermediate drivers are not realized as separate chips but are implemented on the function chip itself.

Abstract: The present invention demonstrates a rotating media storage system which quickly measures and accurately compensates for thermal and mechanical errors in the position of the data detector with respect to the written data. This is accomplished by measuring the error rate of the written data as a function of the read offset of the detector. Error rates become increasingly large as the sensed noise to signal ratio becomes large. The present invention counts the number of errors detected in reading written data for various read offsets when the data storage system is initially activated. When the number of errors reaches a target rate, the read offset required to produce the target rate is saved. This procedure is performed on either side of the data track. The detector is then centered between the two offsets. During the operation of the storage system, thermal and mechanical errors are introduced into the detector position compensation means.

Abstract: An emitter follower output circuit includes a first bipolar transistor for outputting a potential from its emitter to an output terminal and a second bipolar transistor, connected in series to the first bipolar transistor, for feeding a current to the first bipolar transistor. A capacitor connected between a collector of the first bipolar transistor and a base of the second bipolar transistor detects a transitional change of a potential at the collector of the first bipolar transistor and controls a potential at the base of the second bipolar transistor.