Abstract: A method divides a recurrent digital clocking signal into a quotient digital signal having a substantially symmetrical duty cycle within a range of programmable quotients, the quotients being selectable in single increments of the recurrent digital clocking signal within a range as selected by a divisor.

Abstract: A counter cell includes a latch circuit, control circuit, and a pull-up circuit. The laatch circuit is formed of a first clocked half-latch (32), a second clocked half-latch (34) and an inverter (INV1) for storing a binary output signal. The first clocked half-latch (32) is responsive to a first clockk phase signal for transferring the binary output signal from its input to its output. The second clocked half-latch (34) is responsive to a second clock phase signal for transferring binary output signal from its input to its output. The control circuit is responsive to an input complement signal for selectively passing the first clock phase signal to the first clocked half-latch so as to permit toggling the state of the binary output signal. The pull-up circuit is responsive to the binary output signal and the input complement signal for generating an output complement signal.

Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirection bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches.

Abstract: The pulse generator is provided in a semiconductor integrated circuit device, in the form of a power-on clearing circuit. The generator is comprised of a capacitor chargeable to produce a power-on clearing pulse, a current-flow regulating element for regulatively charging the capacitor to output a state signal, and a voltage detector operative in an active condition for monitoring a level of a rising power source voltage to control the current-flow regulating element and being responsive to the state signal to switch to a rest condition. By such construction, a power-on clearing pulse is stably generated regardless of a rising rate of the power source voltage while eliminating a current consumption after completion of the generation of the power-on clearing pulse.

Abstract: A device for selectively recording charges for copies made on a copying machine by way of two or more accounting means connected at the same time via the device to the copying machine, comprising means for coupling the device to the copying machine, a plurality of connection points each one of which is connectable separately to a different accounting means and control means which selectively activates one of the accounting means for recording of the charges and the method of accomplishing the recording of such charges.

Abstract: A frequency divider includes at least three master-slave flip-flops which are connected to each other in stages, each stage including a master flip-flop and a slave flip-flop, to construct a 1/N frequency divider. At least two outputs whose periods are the same but phases are different are taken out from a master flip-flop and a slave flip-flop and combined to obtain a 1/(N/2) divided output signal. As a result, a divided output signal whose period does not vary with time is obtained and, when the N is an even number, an output signal with a duty ratio of 1/2 is obtained. A pulse signal former includes a differential amplifier to which two signals whose periods and pulse widths are the same but phases are shifted by a pulse width and an output obtained by comparing those two signals is output from the pulse signal former. As a result, an output signal whose duty ratio is 1/2 is obtained.

Abstract: A substrate bias generator for supplying a predetermined substrate bias voltage to a semiconductor device includes a charge circuit in which there is provided a rectifying pMOS transistor formed in an n-well. The n-well is maintained at a negative voltage level during the pumping operation. As a result, the threshold voltage of the rectifying pMOS transistor is prevented from increasing to enable the bias volatge to be supplied at a higher efficiency.

Abstract: A highly stable high-voltage output buffer is provided which may be manufactured using standard CMOS technology. As part of the invention, the effects of voltage drift at one or more of the nodes formed between series connected P or N-channel MOSFET devices are generally reduced or eliminated. The present invention includes compensation circuitry which reduces the effects of parasitic coupling within the MOSFET devices, and which serves to compensate for any voltage drift which may occur at the nodes between series connected devices. In addition, the present invention provides a method and apparatus for increasing the current sourcing capability of a CMOS high-voltage output buffer, even under low supply V.sub.vf conditions, without necessarily increasing the size of the output device. Furthermore, the present invention provides a method and apparatus for reducing the effects of coupling along a shared bias line between a plurality of high-voltage output buffers in accordance with the present invention.

Abstract: A charge-pump circuit implements ramp control, steady-state regulation and trimming of the negative voltage pulses. The circuit includes a negative-voltage charge-pump subcircuit having multiple phase inputs, a phase-enable input, an output, a supply voltage, a reference voltage, a ramp-control subcircuit for controlling the rate of change of the voltage at the output of charge-pump subcircuit, and an amplitude-control subcircuit for controlling the amplitude of the voltage at the output of the charge-pump subcircuit. The ramp-control has an input coupled to the output of the charge-pump subcircuit and an output coupled to the phase-enable input of the charge-pump subcircuit. The amplitude-control subcircuit has an input to the output of the charge-pump subcircuit and has an output coupled to the phase-enable input of the charge-pump subcircuit.

Abstract: A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A follower amplifier is connected to each floating gate storage device and drives an analog output voltage bus. A capacitor is connected to each analog output storage bus. An analog pass gate is connected between each analog output voltage bus and a common monitor/dynamic load bus. Each analog pass gate is driven by a strobe signal.

Abstract: In a driving circuit supplied with an input signal having one of logic one and zero levels and producing an output signal through an output terminal to drive a load circuit connected to the output terminal, a first MOS transistor (26) is put into a first source-drain conductive state to produce a predetermined positive voltage (VDD) as the output signal when the input signal has the logic one level. The first MOS transistor has a first channel between its source and drain terminals. A second MOS transistor (27) is put into a second source-drain conductive state to produce a ground potential as the output signal when the input signal has the logic zero level. The second MOS transistor has a second channel between its source and drain terminals. Each of the first and the second channels has a restricted channel width to restrict source-drain currents flowing through the first and the second channels.

Abstract: A circuit for time stamping event signals, e.g. zero-crossings, using coarse and fine timers. The fine timer is a circuit section which subdivides a period from a phase-locked ring-oscillator into 2N subparts. An event signal is timed by latching a digital representation of a particular subpart. The digital representation of the subpart is an N-bit dual thermometer code which uniquely identifies each subpart with each adjacent subpart differing by only one bit. The subparts are made finer in time quantization than the propagation delay of one active element in the ring oscillator by the use of linear combiner elements. The dual thermometer code, encoded post-latching into a binary code, forms the "fine" timing part of a binary word representation of the event time. The event also latches the count states of a pair of lead-lag counters in a master-slave configuration counting ring oscillator periods. These counters change states respectively before and after the dual thermometer code turn-overs.

Abstract: An output circuit for semiconductor integrated circuit includes an input terminal, an output terminal, a supply terminal, first and second transistors, and first and second drive circuits. One terminal of the first and second transistors are coupled to the power voltage terminal, and the other terminals thereof are coupled to the output terminal. The first drive circuit turns on the first transistor when voltage of the input terminal is in a different logical level from voltage of the supply terminal. The second drive circuit turns on the second transistor when voltage of the input terminal is in a different logical level from the voltage of the supply terminal, and turns off the second transistor when voltage of the output terminal is in the range between a predetermined threshold voltage and the voltage of the supply terminal.

Abstract: A system and method counts the maximum and minimum number of continuous cycles in which a RISC system event occurs. Additionally, a hold enable input offers the functionality of counting max/min events that are not continuous in time. These maximum and minimum counts are useful for benchmarking performance measurements and for performance debugging. The system and method provides a self-test mode for component testing, as well as maximum, minimum, and accumulator counting modes for use in a programmable performance analysis system. These counting modes allow various aspects of a target system to be categorized for performance analysis. The system has applicability in workstations and RISC systems having high frequency requirements typically greater than 50 Mhz.

Abstract: A nine bit Gray code counter is constructed as a single integrated circuit such as a PLA and comprises D flip-flops, AND gates and Exclusive-OR gates. The array is programmed to provide a nine bit Gray code count at its outputs. The Q output of each flip-flop provides one bit in the Gray code count. The D input to each flip-flop is determined by the significance of the bit and the following equations: D0=A XOR Q0; D1=(A.multidot.Q0) XOR Q1; Dn=(A.multidot. . . . .multidot.Qn-2.multidot.Qn--1) XOR Qn; and Dmsb=(A.multidot.Q0.multidot.Q1.multidot. . . . .multidot.Qmsb-2 XOR Qmsb.

Abstract: A bias voltahe generating circuit which is low in power consumption and small in chip size of an IC and does not pickup noises readily. The bias voltage generating circuit comprises a current mirror circuit including a diode-connected first transistor of a first conduction type and second and third transistors of the first conduction type, and bias voltage generating fourth and fifth transistors of a different second conduction type having input electrodes connected to output electrodes of the second and third transistors, respectively. The first to third transistors and the fourth and fifth transistors are formed on a single chip semiconductor substrate as a semiconductor integrated circuit. The bias voltage generating circuit further comprises a resistor provided outside the integrated circuit and connected to an input electrode of the first transistor, and a predetermined bias current is supplied to the first transistor through the resistor.

Abstract: A phase lock loop monitors the frequency of redundant input clock signals and switches back and forth therebetween should one or the other become invalid. Thus, the PLL may continue normal operation even with a failure of one input clock signal. If both the input clock signals fail, an internal reference signal maintains the PLL at a nominal operating frequency until one of the input clock signals is restored whereby the loop can quickly re-establish phase lock. To determined validity, the input clock signals are sampled and stored by the reference signal in a predetermined manner. The input clock signal is valid if the samples of the input clock signal each have the same logic state after the sampling period; otherwise, the input clock signal is invalid if the samples of the input clock signal have at least one different logic state after the sampling period.

Abstract: A power unit assembly comprising an internal-combustion engine, a mechanical, unsynchronized gearbox, a clutch interposed between the engine and the gearbox, an inertia brake in which the gearbox, the relevant synchronization by means of the engine or the inertia brake and the control of the injection pump for the engine are controlled by an electronic processor adapted to inhibit the engagement of gear ratios to which an engine speed corresponds which does not fall within a programmed range of normal values; the processor is adapted to detect emergency operating conditions and, in such a case, to allow the engagement of a gear ratio which results in an engine speed value above said programmed range of values; to ensure synchronization even under such conditions the injection pump is provided with adjustment means adapted to allow speeds to be attained which are close to the upper limit of mechanical integrity of the engine.

Abstract: A level shifter, particularly suited for driving power stages for supplying power to integrated circuits, includes a DMOS transistor (40) which is driven by a digital signal source (42) and has a load resistor (44) as its drain load. A shifted output signal develops at the ends of said load resistor. The drain (V1) of the DMOS transistor is connected to the input of an inverter (46), while a Zener diode (54) and a second transistor (52) are connected in parallel with the load resistor (44), the gate of the second transistor (52) being driven by the output of the inverter (46). The output of the inverter (46) can be connected to the input of a drive stage (48), the output of which drives a power stage (50) for supplying power to an integrated circuit.

Abstract: A circuit to generate a power up reset pulse for a semiconductor device, such as a dynamic random access memory (DRAM) that may utilize an on chip voltage generator is disclosed. The circuit generates a positive going pulse when the external power supply ramps up. The pulse disappears when the voltage level within the device reaches a predetermined value of the external supply voltage. The circuit includes a CMOS inverter that is biased between the external voltage and ground and has its input coupled to the internally regulated voltage. The gate of a pull down transistor may couple the input of the CMOS inverter to the internally regulated voltage. A pull up transistor that is biased by the external voltage and whose gate is connected to the output of the CMOS inverter, is connected to the input of the CMOS inverter. Other elements may be added to enhance the circuits performance.