Abstract: A light-emitting device includes a first light-emitting element, a second light-emitting element having a peak emission wavelength different from that of the first light-emitting element, a light-guide member covering a light extracting surface and lateral surfaces of the first light-emitting element and a light extracting surface and lateral surfaces of the second light-emitting element, and a wavelength conversion layer continuously covering the light extracting surface of each of the first and second light-emitting elements and disposed apart from each of the first and second light-emitting elements, and a first reflective member covering outer lateral surfaces of the light-guide member. An angle defined by an active layer of the first light-emitting element and an active layer of the second light-emitting element is less than 180° at a wavelength conversion layer side.

Abstract: The present subject matter relates to an integrated circuit. The integrated circuit includes a first metal layer and a second metal layer capacitively coupled to the first metal layer through a dielectric layer. Further, the second metal layer includes an electron leakage path to provide for leakage of charge from the second metal layer in a predetermined leak time period.

Abstract: A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region.

Abstract: A pixel structure includes a light emitting diode chip and a light blocking structure. The light emitting diode chip includes a P-type semiconductor layer, an active layer, an N-type semiconductor layer, a first electrode, and K second electrodes. The active layer is located on the P-type semiconductor layer. The N-type semiconductor layer is located on the active layer. The N-type semiconductor layer has a first top surface that is distant from the active layer. The first electrode is electrically connected to the P-type semiconductor layer. The light blocking structure is located in the light emitting diode chip and defines K sub-pixel regions. The active layer and the N-type semiconductor layer are divided into K sub-portions respectively corresponding to the K sub-pixel regions by the light blocking structure. The K sub-pixel regions share the P-type semiconductor layer.

Abstract: A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

Abstract: Provided is a Schottky barrier diode which is configured from a Ga2O3-based semiconductor, and has a lower rising voltage than a conventional one. In one embodiment, the Schottky barrier diode 1 is provided which has: a semiconductor layer 10 configured from a Ga2O3-based single crystal; an anode electrode 11 which forms a Schottky junction with the semiconductor layer 10, and has a portion which contacts the semiconductor layer 10 and is composed of Fe or Cu; and a cathode electrode 12.

Abstract: Certain embodiments include a cubic boron nitride (c-BN) device. The c-BN device includes a n/n+ Schottky diode and a n/p/n+ bipolar structure. The n/n+ Schottky diode and the /p/n+ bipolar structure are on a single-crystal diamond platform.

Abstract: A vertical memory device includes a substrate, a plurality of gate electrodes vertically stacked over the substrate in a cell array region, and a plurality of multi-layered pad portions formed over the substrate in a contact region. Each multi-layered pad portion of the plurality of multi-layered pad portions extends from an end of a gate electrode of the plurality of gate electrodes. Each multi-layered pad portion of the plurality of multi-layered pad portions includes a lower pad, an upper pad spaced vertically apart from the lower pad, a buffer pad formed between the lower pad and the upper pad, and a pad interconnection portion interconnecting the lower pad and the upper pad.

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

Abstract: A semiconductor light-emitting device comprises a semiconductor stack having a first surface, wherein the first surface comprises multiple protrusion portions and multiple concave portions; a first electrode on the first surface and electrically connecting with the semiconductor stack; a second electrode on the first surface and electrically connecting with the semiconductor stack; and a transparent conduction layer conformally covering the first surface and between the first electrode and the semiconductor stack, wherein the first electrode comprises a first bonding portion and a first extending portion, and the first extending portion is between the first bonding portion and the transparent conduction layer and conformally covers the transparent conduction layer.

Abstract: The disclosure relates to an LED display module, and more particularly to an LED display module, in which a conductive metal thin film layer formed by deposition is used to configure lateral side wiring for connecting an upper circuit pattern and a lower circuit pattern of a substrate, thereby removing a bezel, and guaranteeing display quality because a division line or a bezel line is not seen even when a plurality of modules undergoes tiling to get a desired display size.

Abstract: An electrode and an organic electroluminescent device using the same are provided. The electrode comprises a first conductive layer (1), a second conductive layer (2) and a third conductive layer (3) that are arranged in a stacked manner The second conductive layer (2) has a single-layer structure or multi-layer composite structure formed by at least one of alkali earth metal, alkali earth metal alloy and alkali earth metal compound, and the third layer (3) has a work function of less than 3 eV. The respective conductive layers of the electrode can compensate with respect to the defects in one another, thereby making the performance of the electrode more stable. In the meantime, because the work function of the third conductive layer (3) is less than 3 eV, the barrier of organics-metal interface can be effectively reduced for guiding the electron injection, thereby increasing the light-emitting efficiency of device.

Abstract: Some embodiments include an integrated structure having a conductive region which contains one or more elements from Group 2 of the periodic table. Some embodiments include an integrated structure which has a conductive region over and directly against a base material. The conductive region includes one or more elements from Group 2 of the periodic table, and has a pair of opposing sidewalls along a cross-section. A capping material is over and directly against the conductive region. Protective material is along and directly against the sidewalls of the protective region.

Abstract: Fabrication schemes based on triblock copolymers for forming self-aligning vias or contacts for back end of line interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate. The method also includes forming a triblock copolymer layer above the lower metallization layer. The method also includes segregating the triblock copolymer layer to form a first segregated block component over the dielectric lines of the lower metallization layer, and to form alternating second and third segregated block components disposed over the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.

Abstract: A substrate processing technique includes: a first heating device configured to heat a substrate to a first processing temperature; a first process chamber provided with the first heating device; a second heating device configured to heat the substrate to a second processing temperature utilizing microwaves, the second processing temperature being higher than the first processing temperature; a second process chamber provided with the second heating device; a substrate placement portion configured to load and unload the substrate with respect to the first process chamber and the second process chamber by placing and rotating the substrate; and a controller configured to respectively control the first heating device, the second heating device, and the substrate placement portion.

Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.

Abstract: A Micro LED display panel, a method for fabricating the Micro LED display panel and a display device are provided. When the LED chip array is transferred, it may only be required to embed the LED chip array into the adhesive film layer. The LED chip array is bonded to the array substrate through the adhesive film layer. Then, unnecessary portions of the adhesive film layer and unnecessary LED chips are removed. It is not necessary to attach LED chips in the LED chip array one by one to the substrate by soldering, in which case the process of fabricating the Micro LED display panel is simplified, the difficulty in fabricating the Micro LED display panel is reduced, the influence of the high temperature generated by the soldering process on the LED chips is avoided, and damage to the LED chips during the transfer process is avoided.

Abstract: Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the semiconductor devices includes a substrate, a gate stack over the substrate and a strained layer in a recess of the substrate and aside the gate stack. Besides, a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.

Abstract: A power MOSFET having a substrate that has a substrate surface into which a trench structure is introduced, wherein first trenches and second trenches form the trench structure. The first trenches and second trenches are arranged in alternation. The first trenches are filled at least partially with a first material and the second trenches are filled with a second material. The first material has a first conductivity type and the second material has a second conductivity type, the first conductivity type and the second conductivity type being different from each other.