Abstract: A read-disturb-based read temperature time-based attenuation system includes a storage device that is coupled to a global read temperature identification subsystem. The storage device determines current read disturb information for data stored in a block in the storage device during a current time period, processes the current read disturb information and previous read disturb information that was determined during at least one previous time period that was prior to the current time period in order to generate a read temperature for the data stored in the block, generates a local logical storage element read temperature map that includes the read temperature, and provides the local logical storage element map to the global read temperature identification subsystem.

Abstract: A system performs verification of Ethernet hardware. A data frame including a first portion for storing a checksum value and a second portion for storing a timestamp value is received. The second portion of data frame is set to zero. A timestamp value for including in second portion of the data frame is received. A modified checksum value is determined based on the checksum value included in the first portion of the data frame and the timestamp value. A cyclic redundancy check (CRC) value is determined for the data frame by nullifying the checksum value in the data frame and considering the timestamp value. A final CRC value is determined by combining the CRC value for the data frame and a CRC correction value based on the checksum. The modified data frame is sent for processing using an emulator.

Abstract: A low-complexity selective mapping method using cyclic redundancy check is provided. In performing coding, a transmitter adds a check bit to information bits to be transmitted to obtain modulated data. Demodulation is performed on an M-order modulation symbol received by a receiver to obtain a decoding result of a coding polynomial of the modulation symbol and bit information received by the receiver. A modulo-2 division result of the decoding result of the coding polynomial and a generation polynomial is calculated. In a case that a remainder of the modulo-2 division result is equal to zero, if the modulated data corresponding to the same index value of the receiver and the transmitter are identical, a current iteration is stopped, and a current value is outputted as a phase rotation sequence index recovery value. Finally, the receiver obtains a decoded signal.

Abstract: A memory view generator evaluates a Liberty file characterizing an NVM module to generate a memory view file for the NVM module. The memory view file includes a port alias identifying ports of the NVM module. The port alias for a set of ports of the NVM module characterizes a type of port in the set of ports. The memory view file includes a port action identifying ports of the NVM module that have a static value and a port access identifying ports of the NVM module that have a dynamic value. The memory view file has an address limit characterizing a number of words in the NVM module and an address partition characterizing address bits and data bits. The memory view file includes a read delay that defines a number of clock cycles needed to hold an address bus stable after a strobe port transitions to an inactive state.

Abstract: Mechanisms are provided to receive encoded header information stored on a tape of a tape drive, wherein the encoded header information has been generated by: generating, for a plurality of tracks of the tape of the tape drive, a header information in a plurality of symbols, wherein the plurality of symbols is comprised of a first set of symbols and a second set of symbols, wherein the first set of symbols include identical information across all tracks of the plurality of tracks, and wherein the second set of symbols are configurable to include different information across all tracks of the plurality of tracks; and modifying, for writing to the tape of the tape drive, the first set of symbols of the plurality of tracks to include parity information corresponding to information included in the second set of symbols of the plurality of tracks. The received encoded header information is decoded.

Abstract: A storage error identification/reduction system includes a storage error identification/reduction subsystem coupled to a storage subsystem including a block. The storage error identification/reduction subsystem receives first data, and writes the first data to first storage locations in the block while writing storage error identification data to second storage location(s) in the block that each are located adjacent at least one of the first storage locations, with the storage error identification data including predetermined values that are written to predetermined locations included in the second storage location(s) in the block. The storage error identification/reduction subsystem then reads the storage error identification data from the second storage location(s) and, based on the predetermined values and predetermined locations of the storage error identification data, identifies errors resulting from the reading of the storage error identification data.

Abstract: A user station for a serial bus system. The user station includes a communication control device for controlling a communication of the user station with at least one other user station, and a transceiver device to serially transmit a transmission signal generated by the communication control device onto a bus and to serially receive signals from the bus. The communication control device generates the transmission signal according to a frame, and inserts a header check sum into the frame, only bits of a frame header that is situated in front of a data field provided for useful data in the frame being included in the computation. For computing the header check sum, the communication control device uses a predetermined starting value and a predetermined check sum polynomial.

Abstract: Disclosed are two methods, the first method comprising receiving a plurality of data packets, producing a coded data packet by coding together at least two data packets, wherein at least one of the at least two data packets is comprised in the received plurality of data packets or in a coding buffer, transmitting the at least two data packets to a first subset of legs, transmitting the coded data packets to a second subset of legs, and determining if the at least two data packets are to be duplicated based on, at least partly, one or more of the following: a notification, a condition, or a first indication.

Abstract: Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.

Abstract: Methods, systems, and devices for wireless communications are described. An encoding device (e.g., a user equipment (UE) or a base station) may divide one or more data units (e.g., packet data convergence protocol (PDCP) protocol data units (PDU)) into a set of data blocks. The encoding device may encode the set of data blocks using a fountain code and may generate a set of data units (e.g., radio link control (RLC) PDUs) based on encoding the set of data blocks using the fountain code. The UE may allocate a first subset of the set of data units to a first carrier and a second subset of the set of data units to a second carrier and may transmit the first subset over the first carrier and the second subset over the second carrier.

Abstract: A cyclo-stationary characteristic of a communications channel and/or storage media is determined. The cyclo-stationary characteristic has K-cycles, K>1. Markov transition probabilities are determined that depend on a discrete phase ?=t mod K, wherein t is a discrete time value. An encoder to optimize the Markov transition probabilities for encoding data sent through the communications channel and/or stored on the storage media. The optimized Markov transition probabilities are used to decode the data from the communication channel and/or read from the storage media.

Abstract: Symbols interleaved among a set of codewords can provide an error correction/detection capability to a dual in-line memory module (DIMM) with memory chips having a comparatively larger bus width. Data corresponding to a set of multibit symbols and received from one or more memory devices can be interleaved/distributed with other bits of at least one codeword.

Abstract: A memory system includes a nonvolatile memory including memory cells, and a memory controller. The memory controller is configured to read first data through application of a first read voltage to each of the memory cells, perform a first decoding process with respect to the first data, when the first decoding process fails, perform a tracking process. The tracking process includes reading second data indicating a threshold voltage level of each of the memory cells through application of a plurality of second read voltages to each of the memory cells, and obtaining, with respect to each of the memory cells, likelihood information using the second data. The second read voltages are shifted by a predetermined amount. The memory controller is further configured to perform a second decoding process with respect to the second data using the likelihood information.

Abstract: Embodiments of this application provide data processing methods and apparatuses. One method includes: inputting all bits in a coded bitstream into a first interleaver or a first tone mapper, wherein the coded bitstream is allocated to M resource units (RUs) allocated for a first user, and M is an integer greater than 1, and reordering all bits in the coded bitstream by using the first interleaver or the first tone mapper.

Abstract: Techniques are provided for remote object store error handling. A storage system may store data within one or more tiers of storage, such as a local storage tier (e.g., solid state storage and disks maintained by the storage system), a remote object store (e.g., storage provided by a third party storage provider), and/or other storage tiers. Because the remote object store may not provide the same data consistency and guarantees that the storage system provides for clients such as through the local storage tier, additional validation is provided by the storage system for the remote object store. For example, when data is put into an object of the remote object store, a verification get operation is performed to read and validate information within a header of the object. Other verifications and checks are performed such as using a locally stored metafile to detect corrupt or lost metadata and/or objects.

Abstract: A memory control circuit stores codewords in a memory module configured to limit errors to one wire of a memory interface. A codeword includes a first block with a first data portion and a second block with a second data portion. An error correction code symbol in the second block is used to locate and correct errors in the second block. Some bits of the first block are repurposed as metadata. The remaining bits are used as parity bits for detecting errors in the first block. The second block is merged with the first block before being stored to memory and demerged from the first block in a memory read operation. Demerging causes errors in the first block to create errors in a corresponding location in the second block. The location of errors found in the second block is used to locate and correct parity errors in the first block.

Abstract: Techniques for debugging a circuit including a global counter configured to continuously increment, a comparator configured to transmit a clock stop signal based on a comparison of a comparator value and a counter value of the global counter, and clock stop circuitry configured to receive the clock stop signal and stop a clock signal to one or more portions of the electronic device.

Abstract: A first serial management interface device includes one or more input/output pins and a controller coupled to the one or more input/output pins. The controller receives a first frame from a second serial management interface device via a first input/output pin and generates a first error code based on the first frame received from the second serial management interface device. The controller receives a second frame from the second serial management interface device via a second input/output pin subsequent to receiving the first frame. The second frame includes a second error code. The controller compares the first error code to the second error code to determine whether first error code and the second error code match.

Abstract: A DIMM slot test system without series connection of test board through JTAG and a method thereof are disclosed. A DIMM connector interface of a test board is inserted to a DIMM slot of a circuit board under test, a CPU generates test data or a test signal based on a test signal with JTAG signal format, the CPU transmits test data to a specified CPLD chip through differential pins or IO pins, the specified CPLD chip records the received data as a test result; the CPU transmits the generated test signal to the specified CPLD chip, which then tests power pins or ground pins, reads and records values of the power pins or the ground pins as the test result; the CPU generates and transmits a test result read signal to the specified CPLD chip through the control pins, obtains the test result through data transmission pins.

Abstract: A storage network operates by: issuing a read threshold number of read slice requests to storage units of a set of storage units, where the read threshold number of read slice requests identifies a read threshold number of encoded slices of a set of encoded slices corresponding to a data segment; when one or more other encoded data slices of the read threshold number of encoded slices is not received within a time threshold, facilitating receiving a decode threshold number of encoded slices of the set of encoded slices; decoding the decode threshold number of encoded slices to produce recovered encoded data slices, wherein a number of the recovered encoded data slices corresponds to the read threshold number minus a number of the encoded slices received within the time threshold; and outputting the recovered encoded data slices and the encoded slices of the read threshold number of encoded slices received within the time threshold.