Patents Examined by Shelly Chase
  • Patent number: 11695432
    Abstract: There is provided an apparatus including an acquisition unit that acquires an information block generated from transmission data for a user and subjected to error correction coding, and an interleaving unit that interleaves a bit sequence of the information block using an interleaver unique to the user. The interleaving unit interleaves the bit sequence by interleaving each of two or more partial sequences obtained from the bit sequence.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: July 4, 2023
    Assignee: SONY GROUP CORPORATION
    Inventors: Ryota Kimura, Yifu Tang
  • Patent number: 11695502
    Abstract: A packet processing method includes generating, by a processor of a network device, a first encoding task based on M original packets in a to-be-processed first data stream, where M is a positive integer, and where the first encoding task instructs to encode the M original packets; and performing, by a target hardware engine of the network device and based on the first encoding task, forward error correction (FEC) encoding on the M original packets to obtain R redundant packets, where R is a positive integer.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: July 4, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Qing Chen, Jiyuan Shi, Jie Chen
  • Patent number: 11695508
    Abstract: The present disclosure relates to data processing methods and apparatus. One example method includes obtaining a first data block from first optical path data, adding padding data and the first data block into a target information bit in a first data frame to form target data, encoding the target data to obtain a first code block, and sending the first code block.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: July 4, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Sisi Ou, Zhangwei Lei, Zhiyu Zhu
  • Patent number: 11681577
    Abstract: Disclosed are various approaches for a controller that can generate and use non-stationary polar codes for encoding and decoding information. In one example, a method includes performing, by an encoder of the controller, a linear operation on at least one vector of information to be stored in a memory. The linear operation includes generating a polar encoded representation from the at least one vector of information. The linear operation also includes generating an output using at least one permutation that is based on a statistical characterization analysis of channels of the memory and a channel dependent permutation that is applied to the polar encoded representation. In some aspects, the statistical characterization analysis includes a respective reliability level of each one of the plurality of channels, and the channel dependent permutation includes an ordered permutation that orders the channels according to their respective reliability level.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: June 20, 2023
    Assignee: The Regents of the University of California
    Inventors: Marwen Zorgui, Mohammed Fouda, Ahmed M. Eltawil, Zhiying Wang, Fadi Kurdahi
  • Patent number: 11683123
    Abstract: In a packet processing method, concatenation processing is performed on other original packets other than a largest first packet in a plurality of original packets. Padding processing is performed on a concatenated packet only when a size of the concatenated packet is less than a size of a largest packet, without performing padding processing on each of the other original packets.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: June 20, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jiyuan Shi, Qing Chen, Mingli Zhang
  • Patent number: 11676679
    Abstract: A memory sub-system configured to encode data using an error correcting code and an erasure code for storing data into memory cells and to decode data retrieved from the memory cells. For example, the data units of a predetermined size are separately encoded using the error correcting code (e.g., a low-density parity-check (LDPC) code) to generate parity data of a first layer. Symbols within the data units are cross encoded using the erasure code. Parity symbols of a second layer are calculated according to the erasure code. A collection of parity symbols having a total size equal to the predetermined size can be further encoded using the error correcting code to generate parity data for the parity symbols.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: June 13, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Sanjay Subbarao, James Fitzpatrick
  • Patent number: 11677495
    Abstract: A safety communication device includes: a safety layer parameter acquisition part to acquire a reception bit rate of safety layer data being received per unit time; a threshold value setting part to set a request error rate requested as an upper limit of a bit error rate of the safety layer data received per unit time, on the basis of a request value corresponding to a bit error rate request being requested as an upper limit of an error occurrence probability per bit during data communication in a non-safety network, and a reception bit rate; and a safety monitoring control part to compare the bit error rate of the safety layer data received within a unit time, with the request error rate, and to perform safety control on the basis of a comparison result.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: June 13, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Kiyohito Miyazaki
  • Patent number: 11671201
    Abstract: Provided is a transmission method executed by a transmitting apparatus to transmit a content to a plurality of terminals. The content having transmission count information indicating a number of times the content is to be transmitted by the transmitting apparatus. The transmission method including a first transmission step of generating and transmitting a first transmission signal which transfers at least a first portion of a plurality of data packets including a plurality of content packets, storing data of the content therein, and a plurality of parity packets, generated from the content packets, and a second transmission step of, when the transmission count information of the content indicates a plurality of times, generating a second transmission signal including at least a second portion of the plurality of data packets, and transmitting the second transmission signal during a period which differs from a period during which the first transmission signal is transmitted.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: June 6, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventor: Yutaka Murakami
  • Patent number: 11658771
    Abstract: Methods are described for identifying and acting upon predetermined message patterns during reception of a data stream structured as USB message frames. A first embodiment performs pattern matching between received message bits and one or more predetermined sequences, identifying unscrambled ordered set messages. A second embodiment applies a descrambling operation and performs comparable pattern matching between descrambled received message bits and one or more additional predetermined sequences, identifying scrambled ordered set messages.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: May 23, 2023
    Assignee: KANDOU LABS SA
    Inventors: Filippo Borlenghi, David Stauffer
  • Patent number: 11650876
    Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to read information from a secondary device about whether the secondary device supports parity-protected data communications. The primary device can be configured to selectively send or receive parity-protected data communications depending on a capability of the secondary device to support parity.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: May 16, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Dean E. Walker, Tony Brewer
  • Patent number: 11650877
    Abstract: A method for detecting an address error when reading a bitstream from a memory is proposed, wherein a check is carried out as to whether the bitstream in conjunction with the present read address is a code word of an error code and wherein, should the bitstream in conjunction with the present read address not be a code word of the error code, an address error is subsequently detected provided the error code does not correct an error correctable thereby. Accordingly, an apparatus, a system and a computer program product are specified.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 16, 2023
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Klaus Oberlaender, Christian Badack, Michael Goessel
  • Patent number: 11652577
    Abstract: A system includes a first node, a second node, and a third node, wherein the first node establishes a wireless communication link with the second node to perform wireless communication, and forwards connection information of the wireless communication to the third node; and the third node receives, by listening on the wireless communication link based on the connection information, transmission data sent by the second node to the first node. If an error occurs when the third node receives the transmission data sent by the second node to the first node, the third node interferes with the first node's reception of the transmission data sent by the second node, so that an error is caused when the first node receives the transmission data sent by the second node, and the second node is triggered to perform retransmission.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: May 16, 2023
    Assignee: SHANGHAI WUQI MICROELECTRONICS CO., LTD.
    Inventors: Da Liu, Zhiyong Xu
  • Patent number: 11652573
    Abstract: Error correction in network packets using soft information and modified payloads are disclosed herein. The method can include extracting soft information from copies of a network packet, using the extracted soft information to select K positions in a payload of the network packet, the payload with uncertain values of bits, the selected K positions having largest levels of uncertainty, changing one or more of the uncertain values at the K positions to a selected combination of values to transform the payload to a modified payload of the network packet, generating an error detection code for the modified payload and when the generated error detection code for the modified payload matches the error detection code for the network packet, using the modified payload as a corrected network packet and processing the next network packet.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: May 16, 2023
    Assignee: Aira Technologies, Inc.
    Inventors: RaviKiran Gopalan, Anand Chandrasekher, Yihan Jiang, Arman Rahimzamani
  • Patent number: 11646820
    Abstract: A method and an optical sensor are described herein. The optical sensor may include a communication interface for receiving data from a control unit and for transmitting data to the control unit, a storage unit with at least one register for storing data, and a CRC generator for generating a CRC checksum. The optical sensor may be configured in such a way that when data stored in the storage unit is to be transmitted to the control unit, the communication interface receives from the control unit a device address specific to the optical sensor and an address of a register in which the data to be transmitted is stored. The CRC generator may be initialized using the device address received from the communication interface and/or the register address received from the communication interface, before the CRC generator generates a CRC checksum for the data to be transmitted.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: May 9, 2023
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Andrey Lysov, Tim Boescke
  • Patent number: 11640336
    Abstract: Method and apparatus for intelligent caching, protection and transfers of data between a cache and a main memory in a data storage environment, such as but not limited to a solid-state drive (SSD). A main memory (MM) has non-volatile memory (NVM) cells configured for persistent storage of user data. A fast response cache (FRC) has NVM cells configured to provide storage of first data prior to transfer to the MM. A write cache (WC) has NVM cells configured to provide storage of second data prior to transfer to the MM. A controller directs input data to either the FRC or the WC. A first type of error correction encoding (ECC1) is applied to the first data and a different, second type of error correction encoding (ECC2) is applied to the second data. Data may be sent from the FRC to the MM either directly or through the WC.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: May 2, 2023
    Assignee: Seagate Technology LLC
    Inventors: Ryan J. Goss, Jack V. Anderson, Jonathan M. Henze
  • Patent number: 11625297
    Abstract: A storage device is provided. The storage device includes a memory device including a memory cell array configured to store metadata and main data and a storage controller configured to access the memory device and control the memory device, wherein the storage controller is configured to read data from the memory device at a speed adaptively varying to a first read speed or a second read speed according to a state of the memory device, the second read speed being faster than the first read speed.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jea-Young Kwon, Young-Jin Park, Jae-Kun Lee, Song Ho Yoon, Sil Wan Chang
  • Patent number: 11626888
    Abstract: Provided is a design method and apparatus for quasi-cyclic low-density parity-check (LDPC) encoding. The method includes: performing LDPC encoding on a K-bit information sequence to be encoded according to a parity check matrix of a quasi-cyclic LDPC code to obtain an N-bit LDPC encoded sequence, where the parity check matrix is determined according to a basic matrix and a lifting size Z, and the basic matrix is determined according to the lifting size Z and a coefficient matrix, where K is a positive integer, N is an integer greater than K, and Z is a positive integer.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: April 11, 2023
    Assignee: ZTE Corporation
    Inventors: Liguang Li, Jun Xu, Jin Xu
  • Patent number: 11621802
    Abstract: Disclosed is a method for processing code blocks as implemented by a baseband processor. The method involves performing a cyclic redundancy check on decoded and deinterleaved code blocks until one fails its CRC check. On first failure the baseband processor requests a retransmission of the code blocks and resumes CRC checks on the retransmitted code blocks, beginning at the code block that had failed. In the event of subsequent failures, the baseband processor performs a soft combine on the failed retransmitted block with its original transmitted counterpart. Only if the soft combined code block fails does the baseband processor request another retransmission. In this case, subsequent CRC failures result in soft combines of three corresponding code words, making the process more robust. The method reduces the number of retransmissions as well as the computing resources needed for processing incoming code blocks.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: April 4, 2023
    Assignee: John Mezzalingua Associates, LLC
    Inventors: Rodney Bryant, Stephen Turner, Jeffrey Masters
  • Patent number: 11611356
    Abstract: A low density parity check (LDPC) channel encoding method is used in a wireless communications system. A communication device encodes an input bit sequence by using an LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The base matrix may be one of eight exemplary designs. The encoding method can be used in various communications systems including fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: March 21, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jie Jin, Wen Tong, Jun Wang, Aleksandr Aleksandrovich Petiushko, Ivan Leonidovich Mazurenko, Chaolong Zhang
  • Patent number: 11599412
    Abstract: Systems, methods, and computer-readable media are provided for utilizing distributed erasure encoding in a redundant array of independent disks (RAID) system. An example method can include generating a plurality of virtual redundant array of independent disk (vRAID) stripes, each of the plurality of vRAID stripes including a segment having a plurality of data, each of the plurality of data including metadata, the metadata including a checksum of a corresponding data of the plurality of data, distributing the segment of each of the plurality of vRAID stripes over a plurality of virtual nodes, mapping at least one of logical files, volumes, or objects to the plurality of data chunks and the at least one parity chunk of the plurality of vRAID stripes to avoid write-hole issues, and verifying data integrity of the corresponding data of the plurality of data using the checksum of the corresponding data.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: March 7, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Sandip Agarwala, Shravan Gaonkar