Abstract: The invention relates to a light source (1) comprising a light generating unit (2) like an organic light emitting diode and an outcoupling device (3) for coupling light out of the light generating unit in an outcoupling direction (4). The outcoupling device comprises a first region (5) for facing the light generating unit, a second region (7) having a refractive index being smaller than the refractive index of the first region, and a structured intermediate region (6) between the first region and the second region. The first region is optically homogenous and has a thickness in the outcoupling direction being larger than a coherence length of the light, thereby reducing generally possible wavelength dependent interference effects and, thus, a corresponding degradation of the outcoupling efficiency. The outcoupling efficiency can therefore be increased.

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.

Abstract: The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions.

Abstract: The source/drain of a fully III-V semiconductor or Si-based transistor includes a bottom barrier layer that may be lattice matched to the channel, a lower layer of a wide bandgap III-V material and a top layer of a comparatively narrow bandgap III-V material, with a compositionally graded layer between the lower layer and top layer gradually transitioning from the wide bandgap material to the narrow bandgap material.

Abstract: A light emitting element is provided, including a first electrode layer, a second electrode layer, and an organic light emitting layer sandwiched between the first electrode layer and the second electrode layer. The organic light emitting layer is patterned to include a plurality of light emitting blocks with different densities. In an embodiment, the light emitting blocks are divided into a plurality of light emitting block groups that are arranged in an alternate manner. In another embodiment, a light emitting element includes a first electrode layer, a first organic light emitting layer, a charge generating layer, a second organic light emitting layer, and a second electrode layer sequentially stacked on one another. The first and second organic light emitting layer are patterned to form a plurality of first and second light emitting blocks with different densities, respectively. Thus, the light emitting element generates full-color, gray-scale, three-dimensional, or dynamic images.

Abstract: A method for forming a gate tie-down includes exposing an active area to form trench contact openings and forming trench contacts therein. An etch stop layer is formed on the trench contacts and on spacers of adjacent gate structures. An interlevel dielectric (ILD) is deposited to fill over the etch stop layer. The ILD and the etch stop layer on one side of the gate structure are opened up to provide an exposed etch stop layer portion. The gate structure is recessed to expose a gate conductor. The exposed etch stop layer portion is removed. A conductive material is deposited to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact.

Abstract: Integrated MEMS-CMOS devices and methods for fabricating MEMS devices and CMOS devices are provided. An exemplary method for fabricating a MEMS device and a CMOS device includes forming the CMOS device in and/or over a first side of a semiconductor substrate. Further, the method includes forming the MEMS device in and/or under a second side of the semiconductor substrate. The second side of the semiconductor substrate is opposite the first side of the semiconductor substrate.

Abstract: An organic electroluminescent illuminating device is shown. The device includes, at least on flexible surface light-emitting unit and a single driving unit. The flexible surface light-emitting unit has a flexible substrate and at least one organic electroluminescent element on the flexible substrate. The single driving unit drives the flexible surface light-emitting unit. At least a portion of the flexible surface light-emitting unit is connected to the driving unit.

Abstract: The invention relates to a device for detecting electromagnetic radiation in the THz frequency range, comprising at least one transistor (FET1, FET2), which has a first electrode, a second electrode, a control electrode, and a channel between the first electrode and the second electrode, and comprising an antenna structure. An electrode is connected to the antenna structure such that an electromagnetic signal which lies in the THz-frequency range and which is received by the antenna structure (1) can be fed into the channel between electrodes and the control electrode is connected to an electrode via a capacitor and/or the control electrode and the first electrode or the control electrode and the second electrode have an intrinsic capacitor such that no AC voltage drop occurs between the control electrode and the first electrode or the second electrode.

Abstract: A light emitting device includes a substrate having a top surface, upper and lower metal layers, multiple LED chips, at least one Zener diode, multiple conductive wires and an encapsulant. The top surface includes a central region bounded by an imaginary boundary with a profile conforming to an outline of a circle stacked with a polygon. The central region has a die bonding area corresponding to the circle, and at least one polygonal extension area formed outside the die bonding area. The upper metal layer includes multiple conducting pads surrounding the central region. The LED chips are disposed on the die bonding area. The Zener diode is disposed on the polygonal extension area. The encapsulant is disposed on the substrate and covers the LED chips.

Abstract: An interposer for an electronic circuit chip package may include a substrate, a recess, first conductive vias, and second conductive vias. The substrate may have a first surface, a second surface substantially parallel to and opposite the first surface, a third surface substantially parallel to the first surface and the second surface, and an orthogonal surface that is substantially orthogonal to and intersects the first surface and the third surface. The recess may be formed in the substrate and defined by the third surface and the orthogonal surface. The first conductive vias may pass from the second surface to the first surface. The second conductive vias may pass from the second surface to the third surface.

Abstract: A metal matrix composite having high corrosion resistance even if the coating film deposit amount is low is obtained. A metal matrix composite includes a metal or alloy substrate coated with a molten transition metal oxide glass, wherein the transition metal oxide glass has an n-type polarity. Further, a method for producing a metal matrix composite includes a step of applying a paste containing a transition metal oxide glass, an organic binder, and an organic solvent onto the surface of a metal or alloy substrate, and a step of forming a glass coating film on the substrate by heating to and maintaining a temperature equal to or higher than the softening point of the transition metal oxide glass after the application step, wherein the transition metal oxide glass has an n-type polarity.

Abstract: A low profile strip dual in-line memory module (200) includes a passive interposer support structure (90) with patterned openings (91-97) formed between opposing top and bottom surfaces, a plurality of memory chips (D1-D8) attached to the top and bottom surfaces, and vertical solder ball conductors (98) extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g., 82-86) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.

Abstract: A packaged power electronic device includes a wide bandgap bipolar driver transistor having a base, a collector, and an emitter terminal, and a wide bandgap bipolar output transistor having a base, a collector, and an emitter terminal. The collector terminal of the output transistor is coupled to the collector terminal of the driver transistor, and the base terminal of the output transistor is coupled to the emitter terminal of the driver transistor to provide a Darlington pair. An area of the output transistor is at least 3 times greater than an area of the driver transistor in plan view. For example, an area ratio of the output transistor to the driver transistor may be between about 3:1 to about 5:1. Related devices and methods of fabrication are also discussed.

Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.

Abstract: A storage device includes: a first electrode; a storage layer including an ion source layer; and a second electrode. The first electrode, the storage layer, and the second electrode are provided in this order. The ion source layer includes a chalcogen element, oxygen, and one or more transition metal elements selected from the group of Groups 4, 5, and 6 elements of the Periodic Table.

Abstract: A mechanism for reducing stiction in a MEMS device by decreasing an amount of carbon from TEOS-based silicon oxide films that can accumulate on polysilicon surfaces during fabrication is provided. A carbon barrier material film is deposited between one or more polysilicon layer in a MEMS device and the TEOS-based silicon oxide layer. This barrier material blocks diffusion of carbon into the polysilicon, thereby reducing accumulation of carbon on the polysilicon surfaces. By reducing the accumulation of carbon, the opportunity for stiction due to the presence of the carbon is similarly reduced.

Abstract: Light emitter devices and methods are provided herein. In some aspects, emitter devices and methods provided herein are for light emitting diode (LED) chips, and can include providing a substrate and a plurality of LED chips over the substrate. The devices and methods described herein can further include providing a plurality of integral lenses over the LED chips, where at least some of the lenses can be distorted. In some aspects, the distorted lenses can be compressed towards each other along one or more directions.

Abstract: A semiconductor device includes a capacitor with reduced oxygen defects at an interface between a dielectric layer and an electrode of the capacitor. The semiconductor device includes a lower metal layer; a dielectric layer on the lower metal layer and containing a first metal; a sacrificial layer on the dielectric layer and containing a second metal; and an upper metal layer on the sacrificial layer. An electronegativity of the second metal in the sacrificial layer is greater than an electronegativity of the first metal in the dielectric layer.