Abstract: The present invention provides a method for manufacturing a thin-film transistor. The thin-film transistor has a bottom gate coplanar structure. The method includes the following steps: step (1): providing a substrate (20); step (2): forming a gate terminal (22) on the substrate (20); step (3): forming a gate insulator layer (24) on the gate terminal (22) and the substrate (20); step (4): forming a source/drain terminal (26) on the gate insulator layer (24) and covering the source/drain terminal (26) with a photosensitive material layer (27); step (5): subjecting a surface of the gate insulator layer (24) to a plasma treatment; step (6): removing the photosensitive material layer (27) located on the source/drain terminal (26); and step (7): forming an oxide semiconductor layer (28) on the source/drain terminal (26) and the gate insulator layer (24) and patternizing the oxide semiconductor layer (28).

Abstract: A transparent organic light emitting display device and a method of manufacturing the transparent organic light emitting display device are provided. The transparent organic light emitting display device comprises a plurality of sub pixel regions, each having a emissive area and a transmissive area, a thin film transistor disposed in the emissive area, and an organic light emitting element electrically connected to the thin film transistor. While the emissive area emits light to display image on the display device, the transmissive area allows the external light to be passed through the display device so that objects behind the display device can be viewed simultaneously with the displayed image.

Abstract: A method of forming a magnetic tunnel junction (MTJ) device includes forming a spacer on an exposed side portion of the MTJ device. The method further includes forming an etch-resistant protective coating associated with the MTJ device. The etch-resistant protective coating provides greater etch resistance than the spacer.

Abstract: A display apparatus includes an array of pixels and dummy pixels. A plurality of first lines are connected to the pixels and the dummy pixels. A plurality of repair lines are connected to the dummy pixels and are selectively connected to the pixels. A plurality of second lines are connected to the pixels. At least one dummy line is connected to the dummy pixels. At least one dummy wiring is connected to the at least one dummy line and is selectively connected to one of the second lines.

Abstract: A metal-insulator-semiconductor field-effect transistor (MISFET) includes a SiC layer with source and drain regions of a first conductivity type spaced apart therein. A first gate insulation layer is on the SiC layer and has a net charge along an interface with the SiC layer that is the same polarity as majority carriers of the source region. A gate contact is on the first gate insulation layer over a channel region of the SiC layer between the source and drain regions. The net charge along the interface between the first gate insulation layer and the SiC layer may deplete majority carriers from an adjacent portion of the channel region between the source and drain regions in the SiC layer, which may increase the threshold voltage of the MISFET and/or increase the electron mobility therein.

Abstract: A semiconductor structure having a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrical contacts; and a photolithographic, thickness non-uniformity, compensation feature, disposed on the surface substrate off of the active semiconductor region. In one embodiment the feature comprises pads on the surface of the substrate and off of the active semiconductor region.

Abstract: A semiconductor structure in fabrication includes a n-FinFET and p-FinFET. Stress inducing materials such as silicon and silicon germanium are epitaxially grown into naturally diamond-shaped structures atop the silicon fins of the n-FinFET and p-FinFET areas. The diamond structures act as the source, drain and channel between the source and drain. The diamond structures of the channel are selectively separated from the fin while retaining the fin connections of the diamond-shaped growth of the source and the drain. Further fabrication to complete the structure may then proceed.

Abstract: A method for exposing an electrode terminal covered with an organic film in a light-emitting device without damaging the electrode terminal is provided. In a region of the electrode terminal to which electric power from an external power supply or an external signal is input, an island-shaped organic compound-containing layer is formed and the organic film is formed thereover. The organic film is removed by utilizing low adhesion of an interface between the organic compound-containing layer and the electrode terminal, whereby the electrode terminal can be exposed without damage to the electrode terminal.

Abstract: A stack package including a first semiconductor chip and second semiconductor chip, the first semiconductor chip including first data I/O pads for transmitting data I/O signals, a first flag pad for receiving a flag signal, and a first buffer for controlling a switching operation between the first data I/O pads and an internal circuit of the first semiconductor chip. The second semiconductor chip includes second data I/O pads for transmitting the data I/O signals, a second flag pad for receiving the flag signal, and a second buffer for controlling a switching operation between the second data I/O pads and an internal circuit of the second semiconductor chip. The first data I/O pads are electrically connected to respective ones of the second data I/O pads through first wires, and the first flag pad is electrically connected to the second flag pad through a second wire. Related methods are also provided.

Abstract: A double-sided organic light-emitting diode and manufacturing method thereof, and a display device using double-sided organic light-emitting diode pixel configuration are described. The double-sided organic light-emitting diode includes a first electrode, a first organic semiconductor layer disposed on the first electrode, a shared electrode disposed on the first organic semiconductor layer and electrically connected to the output terminal of a thin film transistor; a second organic semiconductor layer disposed on the shared electrode, and a second electrode disposed on the second organic semiconductor. The first electrode, the shared electrode and the second electrode are electrically insulated from each other, and two organic light-emitting diodes in the double-sided organic light emitting diode can be independently controlled.

Abstract: An organic light-emitting display apparatus includes a display substrate, a display panel on the display substrate and including a pixel region including an organic light-emitting device (OLED), and a non-pixel region, and an encapsulation substrate for encapsulating the display panel, wherein the encapsulation substrate defines at least one groove therein in which a color filer is located.

Abstract: Image sensor package structure and method are provided. The method includes: providing first substrate having upper surface on which image sensing areas and pads are formed; providing second substrate having through holes; forming tape film on upper surface of second substrate to seal each through hole; contacting lower surface of second substrate with upper surface of first substrate to make image sensing areas in through holes; removing portions of tape film and second substrate, wherein remained tape film and second substrate form cavities including sidewalls made of second substrate and caps sealing sidewalls and made of tape film, and remained second substrate also covers pads; removing portions of remained second substrate to expose pads; slicing first substrate to form single image sensor chips including image sensing areas and pads; and electrically connecting pads with circuits on third substrate through wires. Pollution or damage to image sensing areas may be avoided.

Abstract: Provided is an organic light-emitting display device that includes: a substrate; a first wiring that extends in a first direction on the substrate and comprises first and second portions with an opening therebetween; a second wiring that overlaps with the opening and extends in a second direction that crosses the first direction; an insulating film that covers the first wiring and the second wiring and comprises a first contact hole that exposes the first portion of the first wiring and a second contact hole that exposes the second portion; and a bridge electrode that is formed on the insulating film, is electrically connected to the first and second portions through the first and second contact holes, and comprises a transparent conductive oxide and a metal.

Abstract: A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour.

Abstract: The present invention provides a semiconductor device in which the threshold voltage of NMOS and the threshold voltage of PMOS are independently controllable, and a method for fabricating the same. The method includes: forming a gate insulating film over an NMOS region and a PMOS region of a semiconductor substrate; forming a carbon-containing tungsten over the gate insulating film formed over one of the NMOS region and the PMOS region; forming a carbon-containing tungsten nitride over the gate insulating film formed over the other one of the PMOS region or the NMOS region; forming a tungsten film over the carbon-containing tungsten and the carbon-containing tungsten nitride; post-annealing the carbon-containing tungsten and the carbon-containing tungsten nitride; and etching the tungsten film, the carbon-containing tungsten, and the carbon-containing tungsten nitride, to form a gate electrode in the NMOS region and the PMOS region.

Abstract: Provided is a method for manufacturing a semiconductor device so as not expose a semiconductor layer to moisture and the number of masks is reduced. For example, a first conductive film, a first insulating film, a semiconductor film, a second conductive film, and a mask film are formed. The first mask film is processed to form a first mask layer. Dry etching is performed on the first insulating film, the semiconductor film, and the second conductive film with the use of the first mask layer to form a thin film stack body, so that a surface of the first conductive film is at least exposed. Sidewall insulating layers covering side surfaces of the thin film stack body are formed. The first conductive film is side-etched to form a first electrode. A second electrode layer is formed with the second mask layer.

Abstract: Different strain-inducing semiconductor alloys may be incorporated into the drain and source areas of different transistors in sophisticated semiconductor devices by at least patterning the corresponding cavities in a common manufacturing sequence. Thus, the etch process may be performed on the basis of a high degree of uniformity and the subsequent epitaxial growth processes may, in some illustrative embodiments, be accomplished on the basis of only one additional lithography step.

Abstract: A semiconductor device in which deterioration of electrical characteristics which becomes more noticeable as the transistor is miniaturized can be suppressed is provided. The semiconductor device includes an oxide semiconductor stack in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are stacked in this order from the substrate side over a substrate; a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor stack; a gate insulating film over the oxide semiconductor stack, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating film. The first oxide semiconductor layer includes a first region. The gate insulating film includes a second region. When the thickness of the first region is TS1 and the thickness of the second region is TG1, TS1?TG1.

Abstract: In a metallization system of a complex semiconductor device, metal pillars, such as copper pillars, may be formed in a nail-like configuration in order to reduce the maximum mechanical stress acting on the metallization system while providing a required contact surface for connecting to the package substrate. The nail-like configuration may be obtained on the basis of appropriately configured resist masks.

Abstract: A method of forming raised S/D regions by partial EPI growth with a partial EPI liner therebetween and the resulting device are provided. Embodiments include forming groups of fins extending above a STI layer; forming a gate over the groups of fins; forming a gate spacer on each side of the gate; forming a raised S/D region proximate to each spacer on each fin of the groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface; forming a liner over and between each raised S/D region; removing the liner from the top surface of each raised S/D region and from in between a group of fins; forming an overgrowth region on the top surface of each raised S/D region; forming an ILD over and between the raised S/D regions; and forming a contact through the ILD, down to the raised S/D regions.