Abstract: An array substrate, a method of manufacturing the same, and a display device are provided. In the array substrate of the present disclosure, the gate cutout is formed in the area where the gate line intersects the data line. The array substrate can reduce the coupling capacitance between the data line and the gate line. When the gate cutout extends beyond the area between the first thin film transistor and the second thin film transistor, the mutual interference between two thin film transistors of each pixel region can be further reduced.

Abstract: A semiconductor structure includes a HV NMOS structure. The HV NMOS structure includes a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The source region and the drain region are separated from each other. The channel region is disposed between the source region and the drain region. The channel region has a channel direction from the source region toward the drain region. The gate dielectric is disposed on the channel region and on portions of the source region and the drain region. The gate electrode is disposed on the gate dielectric. The gate electrode includes a first portion of n-type doping and two second portions of p-type doping. The two second portions are disposed at two sides of the first portion. The two second portions have an extending direction perpendicular to the channel direction.

Abstract: Display panel configurations are described in which a pixel-level integrated black matrix layer is combined with an elliptical polarizer. The elliptical polarizer may allow for increased transmission of emissive LEDs in the display panel, while the black matrix layer may mitigate internal reflection of ambient light.

Abstract: Integrated circuit structures and methods for forming the same are provided. An integrated circuit includes a dielectric layer in a memory region and a logic region. The integrated circuit structure also includes a first conductive feature in the dielectric layer in the memory region. The integrated circuit structure further includes a second conductive feature in the dielectric layer in the logic region. In addition, the integrated circuit structure includes an active memory cell over the dielectric layer in the memory region. The active memory cell is connected to the first conductive feature. The integrated circuit structure also includes a dummy memory cell over the dielectric layer in the logic region. The dummy memory cell is connected to the second conductive feature.

Abstract: An Electro-Static-Discharge (ESD) protection device has a Silicon-Controlled Rectifier (SCR) with a triggering PMOS transistor. The SCR is a PNPN structure with a P+ anode/source within a center N-well, a P-substrate, and an outer N-well that connects to a cathode using N+ well taps. The P+ anode/source is both the source of the triggering PMOS transistor and the anode of the SCR. A trigger circuit drives the gate of the triggering PMOS transistor low, turning it on to charge the P+ drain. Since the P+ drain straddles the well boundary, making physical contact with both the center N-well and the P-substrate, holes flow into the P-substrate. The P+ drain is located near guard rings that suppress latch-up. The holes from the P+ drain flood the region under the guard rings, temporarily weakening their effect and reducing the trigger voltage.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer.

Abstract: An LED device has a cap containing one or more quantum dot (QD) phosphors. The cap may be sized and configured to be integrated with standard LED packages. The QD phosphor may be held within the well of the LED package, so as to absorb the maximum amount of light emitted by the LED, but arranged in spaced-apart relation from the LED chip to avoid excessive heat that can lead to degradation of the QD phosphor(s). The packages may be manufactured and stored for subsequent assembly onto an LED device.

Abstract: A thin film transistor substrate includes a switching element comprising a gate electrode electrically connected to a gate line extending in a first direction, an active pattern overlapping with the gate electrode, a source electrode disposed on the active pattern and electrically connected to a data line extending in a second direction crossing the first direction, and a drain electrode spaced apart from the source electrode. The thin film transistor substrate further includes an organic layer disposed on the switching element, a first electrode disposed on the organic layer, and a second electrode overlapping with the first electrode, and electrically connected to the drain electrode. A thickness of the second electrode is thicker than a thickness of the first electrode.

Abstract: In the present disclosure, a non-volatile memory cell comprises a data storage unit, a selection unit and a switching unit. The data storage unit is configured to store an information bit and has a first end and a second end. The first end is coupled to a bit line. The selection unit is configured to access the data storage unit, and the selection unit has a first end coupled to a select line, a second end coupled to the second end of the data storage unit, and a third end coupled to a source line. The switching unit is configured to perform a formation operation and has a first end coupled to a forming line and a second end coupled to the second end of the data storage unit.

Abstract: In order to easily inspect a dispersion state of conductive particles in such an anisotropic conductive film that the conductive particles are dispersed even at high density, linear lines including no conductive particle in a plan view of an anisotropic conductive film including an insulating adhesive layer and conductive particles dispersed in the insulating adhesive layer are allowed to exist at predetermined intervals. Specifically, the conductive particles are disposed in a lattice so as to be arranged in a first arrangement direction and a second arrangement direction, and the disappearance lines are inclined relative to the first arrangement direction or the second arrangement direction.

Abstract: Disclosed are structures and methods related to a barrier layer for metallization of a selected semiconductor such as indium gallium phosphide (InGaP). In some embodiments, the barrier layer can include tantalum nitride (TaN). Such a barrier layer can provide desirable features such as barrier functionality, improved adhesion of a metal layer, reduced diffusion, reduced reactivity between the metal and InGaP, and stability during the fabrication process. In some embodiments, structures formed in such a manner can be configured as an emitter of a gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) or an on-die high-value capacitance element.

Abstract: The present invention provides a method of manufacturing a semiconductor device to improve the manufacturing yield of the semiconductor device. The manufacturing method includes the steps of: forming a groove extending in a first direction (y direction) across a first power transistor formation region and a second power transistor formation region, in a back surface of a semiconductor wafer; filling the groove with a conductor film by forming the conductor film on the back surface in which the groove is formed; and exposing the back surface of the semiconductor wafer by removing a portion of the conductor film.

Abstract: It is the object of the invention to provide a power semiconductor rectifier with a low on-state-voltage and high blocking capability. The object is attained by a power semiconductor rectifier comprising: a drift layer having a first conductivity type; and an electrode layer forming a Schottky contact with the drift layer, wherein the drift layer includes a base layer having a peak net doping concentration, below 1·1016 cm?3 and a barrier modulation layer which is in direct contact with the electrode layer to form at least a part of the Schottky contact, wherein a net doping concentration of the barrier modulation layer is in a range between 1·1016cm?3 and 1·1019 cm?3 and wherein the barrier modulation layer has a layer thickness in a direction vertical to the interface between the electrode layer and the barrier modulation, layer of at least 1 nm and less than 0.2 ?m.

Abstract: Disclosed herein are methods for additive formation of a STT-MRAM metal stack using a deposition process through a pre-patterned template that skims away metal ions that are less likely to enable anisotropic deposition on a substrate. The pre-patterned template is formed from a film stack using patterning techniques to form an opening in the film stack that exposes portions of an underlying substrate where a MTJ will be formed for an MRAM cell. The film stack cavity may be exposed to etch processes that selectively pull back the sidewall, such that other layers in the film stack protrude into the cavity. Additional treatments to the other layers may alter the opening sizes in the other layers. Metal deposited through the cavity such that metal ions with anisotropic characteristics will be skimmed away before reaching the substrate.

Abstract: A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.

Abstract: A semiconductor module includes a base substrate, a semiconductor element provided on the front surface side of the base substrate, and a resin case bonded to the front surface of the base substrate and enclosing a region in which the semiconductor element is provided, wherein the resin case has a depressed portion formed in a height direction away from the base substrate in a bottom surface bonded to the base substrate, and a connection hole that connects the depressed portion and the exterior of the resin case.

Abstract: A method of manufacturing a light emitting element includes forming a resin film including a phosphor containing layer on a transparent board side surface of a wafer including a transparent board and a plurality of light emitting parts formed on the transparent board, forming a scribing line along a scheduled separation surface in a surface of the transparent board by scribing before or after forming the resin film, cutting the resin film along the scheduled separation surface before or after forming the scribing line, and separating the transparent board along the scheduled separation surface by breaking after forming the scribing line and cutting the resin film.

Abstract: A finFET semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first fin formed in a first semiconducting layer, a second fin formed in a second semiconducting layer, and an insulating layer disposed between the first fin and the second fin. The first fin, the second fin, and the insulating layer form a stacked structure above a substrate.

Abstract: A method for fabricating an electronic device including a semiconductor memory may include: forming a first interlayer dielectric layer over a substrate to have an opening exposing the substrate; forming a bottom electrode in a portion of the opening to have an exposed top surface; forming a variable resistance material layer along sidewalls of the remaining portion of the opening and the exposed top surface of the bottom electrode; forming a top electrode over the variable resistance material layer so as to fill the opening; etching the first interlayer dielectric layer to a predetermined depth to expose a part of the variable resistance material layer surrounding sidewalls of the top electrode; and removing the part of the variable resistance material layer to form a unit cell.

Abstract: A method of fabricating a semiconductor device includes forming first and second fin patterns in an active region and in a measurement region of a substrate, respectively, the measurement region being different from the active region, forming first and second gate electrodes to cross the first and second fin patterns, respectively, and measuring a contact potential difference (Vcpd) of the second gate electrode to determine a threshold voltage of the first gate electrode based on the measured contact potential difference (Vcpd).