Abstract: A method includes forming a trench that is partially filled with a first metal material, the trench being formed within a first Interlayer Dielectric (ILD) layer, filling a remaining portion of the trench with a sacrificial material, depositing a buffer layer on the first ILD layer, patterning the buffer layer to form a hole within the buffer layer to expose the sacrificial material, and removing the sacrificial material.

Abstract: An embodiment of a transistor includes a semiconductor substrate, spaced-apart source and drain electrodes coupled to the semiconductor substrate, a gate electrode coupled to the semiconductor substrate between the source and drain electrodes, a dielectric layer over the gate electrode and at least a portion of the semiconductor substrate, and a field plate structure over the dielectric layer, wherein the field plate structure includes a gold-containing material and one or more migration inhibiting materials.

Abstract: A semiconductor device in which the aperture ratio and which includes a capacitor with increased charge capacity is provided. A semiconductor device in which the number of masks used in a manufacturing process is reduced and the manufacturing costs are reduced is also provided. An impurity is contained in a light-transmitting semiconductor film so that the semiconductor film functions as one of a pair of electrodes in a capacitor. The other pair of electrodes is formed using a light-transmitting conductive film such as a pixel electrode. Further, a scan line and a capacitor line are provided on the same surface and in parallel to each other. An opening reaching the capacitor line and an opening reaching a conductive film which can be formed in the formation of a source electrode or a drain electrode of the transistor can be formed concurrently in an insulating film.

Abstract: A method of reducing line bending and surface roughness of a substrate with pillars includes forming a treated surface by treating a pillar-containing substrate with a radical. The radical may be silicon-based, nitrogen-based or oxygen-based. The method may include forming a dielectric film over the treated surface by reacting an organosilicon precursor and an oxygen precursor. The method may include curing the dielectric film at a temperature of about 150° C. or less. A method of reducing line bending and surface roughness of a substrate with pillars includes forming a dielectric film over a pillar-containing substrate by reacting an organosilicon precursor, an oxygen precursor, and a radical precursor. The method may include curing the dielectric film at a temperature of about 150° C. or less. The radical precursor may be selected from the group consisting of nitrogen-based radical precursor, oxygen-based radical precursor, and silicon-based radical precursor.

Abstract: A complementary metal oxide semiconductor (CMOS) device includes a p-channel metal oxide semiconductor (PMOS) transistor unit and an n-channel metal oxide semiconductor (NMOS) transistor unit. A semiconductor layer of the PMOS transistor unit between source and drain electrodes thereof is divided into a first tapered region having an ion concentration of CP/e and a first flat region having an ion concentration of CP/f. A semiconductor layer of the NMOS transistor unit between source and drain electrodes thereof is divided into a second tapered region having an ion concentration of CN/e, a second flat region having an ion concentration of CN/f?2 and a third flat region located between the second tapered region and second flat region and having an ion concentration of CN/f?1, wherein the ion concentrations have a relationship of CP/e<CP/f<CN/f?2<CN/e<CN/f?1.

Abstract: A color filter array and micro-lens structure for imaging system and method of forming the color filter array and micro-lens structure. A micro-lens material is used to fill the space between the color filters to re-direct incident radiation, and form a convex micro-lens structure above a top surface of the color filters.

Abstract: A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines.

Abstract: Provided are organic luminescence display and method for manufacturing the same. According to an aspect of the present invention, there is provided an organic luminescence display comprising a substrate and a plurality of pixels disposed on the substrate. The pixels comprise a plurality of first pixels, each comprising a first organic light-emitting layer, and a plurality of second pixels which are smaller than the first pixels and each of which comprises a second organic light-emitting layer. The surface roughness of the second organic light-emitting layer is greater than the surface roughness of the first organic light-emitting layer.

Abstract: A semiconductor device includes a substrate with cell and peripheral regions and capacitors provided on the cell region. The cell region may include a plurality of sub-cell blocks, which are spaced apart from each other by a plurality of sub-peripheral regions, and on which the capacitors are provided. Each of the sub-peripheral regions may have a width that is two to five times a distance between centers of an adjacent pair of the capacitors.

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

Abstract: An ion sensor apparatus comprises at least one ion sensitive field effect transistor (ISFET) device configured to be exposed to a liquid, a reference electrode configured to contact the liquid to which the ISFET device is exposed, and at least one magnet configured to intermittently expose the ISFET device to a magnetic field. A processor is operatively connected to the ISFET device and the reference electrode. The processor modulates the magnetic field to produce a corresponding modulated output in resistance of the ISFET device, and modulation of a reported output value of the ion sensor apparatus.

Abstract: A MEMS sensor package comprises a MEMS die that includes a substrate having a sensor formed thereon and a cap layer coupled to the substrate. The cap layer has a cavity overlying a substrate region at which the sensor resides. A port extends between the cavity and a side wall of the MEMS die and enables admittance of fluid into the cavity. Fabrication methodology entails providing a substrate structure having sensors formed thereon, providing a cap layer structure having inwardly extending cavities, and forming a channel between pairs of the cavities. The cap layer structure is coupled with the substrate structure and each channel is interposed between a pair of cavities. A singulation process produces a pair of sensor packages, each having a port formed by splitting the channel, where the port is exposed during singulation and extends between its respective cavity and side wall of the sensor package.

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.

Abstract: A method can be used for producing an optoelectronic component. An optoelectronic semiconductor chip has a front face and a rear face. A sacrificial layer is applied to the rear face. A molded body is formed the optoelectronic semiconductor chip being at least partially embedded in the molded body. The sacrificial layer is removed.

Abstract: A semiconductor device includes: a first plug; a bit line which is in contact with the first plug and over the first plug and extended in one direction; a second plug including a first part adjacent to the bit line and a second part adjacent to the first plug; a double air gap which is disposed between the first part of the second plug and the bit line and includes a first air gap surrounding the first part of the second plug and a second air gap parallel to sidewalls of the bit line; and a capping layer suitable for capping the first and second air gaps.

Abstract: Disclosed herein is a light-emitting device including a plurality of first light-emitting elements mounted in a matrix form on a common wiring board. Each of the first light-emitting elements has a single crystal semiconductor multilayer structure and is a semiconductor element in the form of a chip that emits light in a given band of wavelengths. When attention is focused on the plurality of first light-emitting elements that belong in a given area of all the plurality of first light-emitting elements, the orientations of the common crystal axes of the first light-emitting elements adjacent to each other at least in one of the row and column directions differ.

Abstract: A vacuum sealed MEMS and CMOS package and a process for making the same may include a capping wafer having a surface with a plurality of first cavities, a first device having a first surface with a second plurality of second cavities, a hermetic seal between the first surface of the first device and the surface of the capping wafer, and a second device having a first surface bonded to a second surface of the first device. The second device is a CMOS device with conductive through vias connecting the first device to a second surface of the second device, and conductive bumps on the second surface of the second device. Conductive bumps connect to the conductive through vias and wherein a plurality of conductive bumps connect to the second device. The hermetic seal forms a plurality of micro chambers between the capping wafer and the first device.

Abstract: A microscale device comprises a patterned forest of vertically grown and aligned carbon nanotubes defining a carbon nanotube forest with the nanotubes having a height defining a thickness of the forest, the patterned forest defining a patterned frame that defines one or more components of a microscale device. A conformal coating of substantially uniform thickness at least partially coats the nanotubes, defining coated nanotubes and connecting adjacent nanotubes together, without substantially filling interstices between individual coated nanotubes. A metallic interstitial material infiltrates the carbon nanotube forest and at least partially fills interstices between individual coated nanotubes.