Patents Examined by Stephen Elmore
  • Patent number: 9678682
    Abstract: A system includes non-volatile memory storing firmware and an embedded baseboard management controller (BMC). The BMC includes a BMC volatile memory and a BMC processor coupled to the BMC volatile memory and the non-volatile memory. The BMC processor performs a first method wherein the firmware is obtained from the non-volatile memory, instrumented, and stored on a host computer volatile memory. Also in the first method, separate copies of vital debug information about the instrumented firmware are stored on the BMC volatile memory and the host computer volatile memory. The system further includes a host computer housing the embedded BMC, the host computer volatile memory, and a host computer processor coupled to the host computer volatile memory. The host computer processor performs a second method wherein the instrumented firmware is obtained from the host computer volatile memory and executed.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: Vijay F. G. Lobo, Devender Rao Marri
  • Patent number: 9665297
    Abstract: A processor core is supported by an upper level cache and a lower level cache that receives, from an interconnect fabric, a write injection request requesting injection of a partial cache line of data into a target cache line identified by a target real address. In response to receipt of the write injection request, a determination is made that the upper level cache is a highest point of coherency for the target real address. In response to the determination, the upper level cache and lower level cache collaborate to transfer the target cache line from the upper level cache to the lower level cache. The lower level cache updates the target cache line by merging the partial cache of data into the target cache line and storing the updated target cache line in the lower level cache.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: May 30, 2017
    Assignee: International Business Machines Corporation
    Inventors: Luis E. De La Torre, Bernard C. Drerup, Sanjeev Ghai, Guy L. Guthrie, Alexander M. Taft, Derek E. Williams
  • Patent number: 9652166
    Abstract: According to certain aspects, a system can include a client computing device configured to: in response to user interaction, store an identifier associated with a first tag in association with a first file; and in response to instructions to perform a secondary copy operation, forward the first file, a second file, and the identifier associated with the first tag. The system may also include a secondary storage controller computer(s) configured to: based on a review of the identifier associated with the first tag, identify the first file as having been tagged with the first tag; electronically obtain rules associated with the first tag; perform on the first file at least a first secondary storage operation specified by the rules associated with the first tag; and perform on the second file at least a second secondary storage operation, wherein the first and second secondary storage operations are different.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 16, 2017
    Assignee: COMMVAULT SYSTEMS, INC.
    Inventors: Manas Bhikchand Mutha, Pavan Kumar Reddy Bedadala, Vinit Dilip Dhatrak, Christopher A. Alonzo
  • Patent number: 9653474
    Abstract: A method for fabricating an electronic device including a semiconductor memory may include: forming a stack structure in which an interlayer dielectric layer and a material layer are alternately stacked on a substrate; forming a plurality of holes arranged to have a substantially constant interval while exposing the substrate by passing through the stack structure; forming a channel layer in a first hole of the plurality of holes; forming a dummy layer in a second hole of the plurality of holes; forming a mask pattern on a resultant structure including the dummy layer and the channel layer to expose an area extending in a first direction while overlapping the dummy layer arranged in the first direction; and forming a slit by etching the stack structure using the mask pattern as an etching barrier and removing the dummy layer.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: May 16, 2017
    Assignee: SK hynix Inc.
    Inventor: Hyoung-Soon Yune
  • Patent number: 9645932
    Abstract: A technique for storing metadata changes includes caching metadata changes in a persistent metadata cache. The persistent metadata cache is configured to cache metadata reads and writes directed to a set of internal volumes of the data storage system. A file system can access pages of the persistent metadata cache by specifying an identifier of an internal volume and an offset into that volume to which the metadata changes are directed.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 9, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Jean-Pierre Bono, Philippe Armangau
  • Patent number: 9645921
    Abstract: A start-up method for USB disk with synchronous flash memory includes steps of: (a) writing test data into a data cache zone of a flash memory according to an initiate read write clock of a flash memory controller; (b) reading the test data to a memory zone of a USB controller; (c) comparing the test data in two memory zones, and recording a comparison result and a phase parameter of read write clock; (d) delaying the initiate read write clock for one-unit delay, and repeating steps (a)˜(d); (e) if the comparison result changes from success to failure, stopping repeat the step (d); (f) selecting the phase parameter of the read write clock that corresponds to one of the comparison results in an interval with multiple continuous successful comparison results to determine a clock phase for accessing the flash memory, and then starting up the USB flash disk. The method is quick and stable.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: May 9, 2017
    Assignee: IPGOAL MICROELECTRONICS (SICHUAN) CO., LTD.
    Inventor: Jian Tang
  • Patent number: 9645940
    Abstract: Various systems, methods, apparatuses, and computer-readable media, for accessing a storage device are described. In certain example embodiments, an active/active fault tolerant storage device comprising two or more controllers may be implemented. In one embodiment, each controller may be coupled to the non-volatile memory’ (NVM) blades comprising the non-volatile memory (NVM) storage medium. In one example implementation, a standardized protocol, such as Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: May 9, 2017
    Assignee: Skyera, LLC
    Inventors: Radoslav Danilak, William Radke
  • Patent number: 9632724
    Abstract: A method and system for storage copy with chain cloning are provided, including providing a volume with one or more snapshots in the form of a dependency chain, where the volume and one or more snapshots are volume nodes in the dependency chain and providing associated metadata required to maintain the one or more snapshots; cloning the dependency chain to create at least one a sparse copy chain including sparse copies of the volume and the one or more snapshots resulting in sparse volume nodes, resulting in a lattice structure of the dependency chain of volume nodes and one or more sparse copy chains of cloned volume nodes.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Christopher B. E. Beeken, Joanna K. Brown
  • Patent number: 9619350
    Abstract: An information handling system may include a processor and a first storage management console comprising a program of executable instructions embodied in non-transitory computer-readable media accessible to the processor, and configured to, when read and executed by the processor: (i) manage input/output between an application and a primary physical storage controller to perform input/output between the application and a storage resource communicatively coupled to primary physical storage container; (ii) asynchronously mirror application-consistent snapshots of data associated with the application from the primary physical storage controller to a storage virtual controller configured to emulate a physical storage controller such that the storage virtual controller stores the snapshots to remote storage geographically remote from the information handling system; (iii) store metadata associated with the application and data stored to the storage resource and the remote storage; and (iv) copy the metadata to a s
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: April 11, 2017
    Assignee: Dell Products L.P.
    Inventors: Gopakumar Ambat, Yask Sharma
  • Patent number: 9612963
    Abstract: A load request is received to retrieve a piece of data from a location in memory and the load request follows one or more store requests in a set of instructions to store a piece of data in the location in memory. One or more possible locations in a cache for a piece of data corresponding to the location in memory is determined. Each possible location of the one or more possible locations in the cache is determined. It is then determined if at least one location of the one or more possible locations contains data to be stored in the location in memory. Data in one location of the at least one location is loaded, the data in the one location is from a store request of the one or more store requests and the store request is closest in the set of instructions to the load request.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: April 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Khary J. Alexander, Jonathan T. Hsieh, Christian Jacobi, James R. Mitchell
  • Patent number: 9612953
    Abstract: A method for managing non-volatile memory is provided. The method includes determining at least one property of a data and determining to which type of a plurality of types of flash memory to write the data, based on the at least one property of the data. The plurality of types of flash memory includes at least two types having differing numbers of bits per cell. The method includes writing the data to a flash memory of the determined type. A flash manager and a flash storage device are provided.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: April 4, 2017
    Assignee: Pure Storage, Inc.
    Inventors: John Davis, Ethan Miller, Brian Gold, John Colgrove, Peter Vajgel, John Hayes, Alex Ho
  • Patent number: 9607696
    Abstract: A method for writing data, the method may include evaluating current levels of multiple memory cells that belong to a certain set of memory cells or receiving an indication about the current levels of the multiple memory cells; encoding a new data unit to provide an encoded data unit to be written to the multiple memory cells while minimizing an amount of changes in levels of the maximum cell level among the multiple memory cells required for storing the encoded data unit; and writing the encoded data unit to the multiple memory cells.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: March 28, 2017
    Assignee: Technion research and development foundation Ltd.
    Inventors: Yitzhak Birk, Amit Berman
  • Patent number: 9602618
    Abstract: A method and system for dynamic distributed data caching is presented. The system includes one or more peer members and a master member. The master member and the one or more peer members form cache community for data storage. The master member is operable to select one of the one or more peer members to become a new master member. The master member is operable to update a peer list for the cache community by removing itself from the peer list. The master member is operable to send a nominate master message and an updated peer list to a peer member selected by the master member to become the new master member.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: March 21, 2017
    Assignee: Parallel Networks, LLC
    Inventors: Keith A Lowery, Bryan S Chin, David A Consolver, Gregg A DeMasters
  • Patent number: 9594682
    Abstract: A control apparatus sends a data access request to a first memory sharing device, wherein the data access request includes an address of target data. The first memory sharing device determines that the target data is stored in a second memory sharing device according to the address of the target data and an address list. The address list includes corresponding relationships between addresses and memory sharing devices, and first addresses corresponding to the first memory sharing device are different from second addresses corresponding to the second memory sharing device, and forward the data access request to the second memory sharing device. The second memory sharing device obtains the target data based on the address of the target data, and sends the target data to the first memory sharing device. Then the first memory sharing device forwards the target data to the control apparatus.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: March 14, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Liangwei Mo
  • Patent number: 9588704
    Abstract: According to certain aspects, a system can include a client computing device configured to: in response to user interaction, store an identifier associated with a first tag in association with a first file; and in response to instructions to perform a secondary copy operation, forward the first file, a second file, and the identifier associated with the first tag. The system may also include a secondary storage controller computer(s) configured to: based on a review of the identifier associated with the first tag, identify the first file as having been tagged with the first tag; electronically obtain rules associated with the first tag; perform on the first file at least a first secondary storage operation specified by the rules associated with the first tag; and perform on the second file at least a second secondary storage operation, wherein the first and second secondary storage operations are different.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: March 7, 2017
    Assignee: Commvault Systems, Inc.
    Inventors: Manas Bhikchand Mutha, Pavan Kumar Reddy Bedadala, Vinit Dilip Dhatrak, Christopher A. Alonzo
  • Patent number: 9582427
    Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Philip Heidelberger, Hillery C. Hunter, James A. Kahle, Ravi Nair
  • Patent number: 9568971
    Abstract: A storage device includes a non-volatile memory, a volatile memory and a controller. The volatile memory supports a normal mode and a self-refresh mode. The controller is configured to store data for a host in the non-volatile memory while using the volatile memory in the normal mode and, in response to receiving a power-down command from the host, to deactivate at least part of the storage device and to switch the volatile memory from the normal mode to the self-refresh mode.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: February 14, 2017
    Assignee: APPLE INC.
    Inventors: Avraham Poza Meir, Evan R. Boyle, Christopher J. Sarcone, Barak Rotbard
  • Patent number: 9563506
    Abstract: A plurality of storage nodes is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory. The plurality of storage nodes is configured to distribute user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of one of the plurality of storage nodes. A chassis enclosing the plurality of storage nodes includes power distribution, a high speed communication bus and the ability to install one or more storage nodes which may use the power distribution and communication bus in some embodiments. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: February 7, 2017
    Assignee: Pure Storage, Inc.
    Inventors: John Hayes, John Colgrove, Robert Lee, Peter Vajgel, Par Botes
  • Patent number: 9558081
    Abstract: Remote computing resource service providers allow customers to execute one or more applications in a virtual environment on computer systems provided by the computing resource service provider. The virtual machines may be managed by a hypervisor executing on computer systems operated by the service provider. The virtual machines' memory may be protected by a memory obfuscation service and the hypervisor. The memory obfuscation service may enable the virtual machines to maintain at least a portion of sensitive information in an obfuscated format. The virtual machines may request access to the virtual machines' memory, the memory obfuscation service may obtain the requested memory in an obfuscated format and un-obfuscate the memory such that it may be used by the virtual machines.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: January 31, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Apolak Borthakur, Raviprasad Venkatesha Murthy Mummidi
  • Patent number: 9552304
    Abstract: A computer-implemented method includes storing commands and maintaining an order of receipt of the commands in a command processing unit. The commands include address translation cache miss commands that are organized as one or more linked lists and stored in a content-addressable memory (CAM). All nodes within a single linked list include commands having addresses that map to the same hash value. Based on receiving a memory fetch completion indicator for a cache entry for a command in a head node in a linked list, all of the commands in the linked list are returned. The returning includes sending the commands in the linked list to an address translation unit in an order specified by the linked list.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David M. Kauer, Lonny J. Lambrecht, Daniel Ramirez, Zelun Tie