Abstract: Tracking changes amongst unit portions (e.g., blocks or files) of a storage system. A logical time identifier is associated with each unit portion and is included within a logical time identifier structure. When writing to a particular write portion, the mechanism updates the appropriate logical time identifiers, calculates redundancy data of a group of one or more logical time identifiers associated with the unit portion(s) of the write portion. Furthermore, the write portion of the storage system is written. In addition, the corresponding redundancy data for that write portion is written to the logical time identifier structure. Later, for a given write portion, the redundancy data is verified to be consistent or inconsistent with the group of one or more logical time identifiers associated with the write portion. If the redundancy data is not consistent, then a current logical time identifier is assigned to each of the logical time identifiers.

Abstract: Systems and methods maintain cache coherency between storage controllers using input/output virtualization. In one embodiment, a primary storage controller receives write commands over a virtualized interface, stores the write commands in cache memory, tracks a status of the write commands processed from the cache memory, and stores the status in a portion of the cache memory. A backup storage controller includes a backup cache that receives replications of the write commands via direct memory access operations, and stores the replications of the write commands. The primary storage controller makes the status available to a host system. In response to a failure of the primary storage controller, the backup storage synchronizes with the status from the host system, and resumes I/O operations for the logical volume.

Abstract: A host information handling system (IHS) provides virtualization of host channel adapters (HCAs). A hypervisor partitions a system memory of the host IHS into multiple logical partitions (LPARs). A particular LPAR includes a single instance of an operating system. The single instance of the operating system includes a common layer that provides virtualization of physical HCAs and sharing of the physical HCAs by multiple virtual HCAs.

Abstract: This disclosure provides techniques of hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to determine a first shaping level corresponding to applying a first shaping operation to data to be stored to the non-volatile memory. The controller is further configured to, in response to the first shaping level exceeding a threshold, perform a second shaping operation to generate shaped data that corresponds to the data, the shaped data having a second shaping level that is less than the threshold.

Abstract: A storage system is provided. The storage system includes a plurality of storage units, each of the plurality of storage units having storage memory for user data and a plurality of storage nodes, each of the plurality of storage nodes configured to have ownership of a portion of the user data. The storage system includes a first pathway, coupling the plurality of storage units such that each of the plurality of storage units can communicate with at least one other of the plurality of storage units via the first pathway without assistance from the plurality of storage nodes.

Abstract: The invention is directed to a storage device utilizing laptop storage drives and rackmount server adapted to use the same. The storage device includes a body and drive software. The drive and internal portions of the body are adapted to form contact fits. The software of the storage device provides an electronic interface that permits operations of advantageous RAID configurations.

Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.

Abstract: Various systems, methods, apparatuses, and computer-readable media for accessing a storage device are described. In certain example embodiments, an active/active fault-tolerant storage device comprising two or more controllers may be implemented. In one aspect, each controller may have two or more processing entities for distributing the processing of the I/O requests. In one embodiment, the configuration of the components, modules and the controller board may be arranged in a manner to enhance heat dissipation, reduce power consumption, spread the power and work load, and reduce latency. In one embodiment, each controller may be coupled to the non-volatile memory (NVM) blades comprising the non-volatile memory (NVM) storage medium. In one example implementation, a standardized protocol, such as the Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium.

Abstract: A just-in-time storage allocation is initiated for storage at a remote storage device having storage disks. Each of multiple containers comprises a grouping of one or more of the storage disks. The just-in-time storage allocation includes an application profile that includes a priority criteria for the storage of either a priority of performance over efficiency or a priority of efficiency over performance A determination is made of whether at least one container of the multiple containers satisfies the priority criteria based on at least one attribute of the at least one container. The storage is allocated in the at least one container, in response to the at least one container satisfying the priority criteria.

Abstract: A photonics-optimized multi-processor system may include a plurality of processor chips, each of the processor chips comprising at least one input/output (I/O) component. The multi-processor system may also include first and second photonic components. The at least one I/O component of at least one of the processor chips may be configured to directly drive the first photonic component and receive a signal from the second photonic component. A total latency from any one of the processor chips to data at any global memory location may not be dominated by a round trip speed-of-light propagation delay. A number of the processor chips may be at least 10,000, and the processor chips may be packaged into a total volume of no more than 8 m3. A density of the processor chips may be greater than 1,000 chips per cubic meter.

Abstract: A computer-executable method, system, and computer program product of managing a hierarchical data storage system, wherein the data storage system includes a first level of one or more hosts, a second level of one or more storage appliances, and a data storage array, the computer-executable method, system, and computer program product comprising receiving an I/O request from a first host of the one or more hosts, wherein the I/O request relates to a portion of data on the data storage array, analyzing the I/O request to determine a status of the portion of data on the data storage system, based on the determination, providing an update to a second host of the one or more hosts based on the I/O request, wherein the portion of data is cached on the second host of the one or more hosts, and processing I/O request by sending I/O request to data storage array.

Abstract: Data objects are stored on storage devices, taking into account service level agreements or other quality of service parameters. In one aspect, data objects grouped into storage volumes. In addition, the storage devices are classified into different level storage tiers, where higher level storage tiers have higher performance and lower level storage tiers have lower performance. Ranks for the data objects are calculated, based on both a data usage pattern for the data object (e.g., recency and frequency) and on quality of service (QOS) parameters for the storage volume containing the data object. Examples of QOS parameters include service level agreements, priority, minimum and maximum input/output operations per second. The data objects are then stored on storage devices, based on the data objects' ranks and the storage devices' storage tiers.

Abstract: Some embodiments includes an interrupt-driven data transport architecture utilizing a memory channel bus. For example, a first logic component at a first computing device can initiate a data access request involving a second logic component at a second computing device. The first logic component can store request information associated with the data access request in a predefined memory space of a memory module connected via a memory channel bus to the first logic component and the second logic component. The first logic component can then generate a request-ready interrupt signal through one or more redundant pins of the memory channel bus. The second logic component can be triggered by the interrupt signal to read the request information from the predefined memory space. The second logic component can use that information to complete the request.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a non-volatile memory, a connection interface, and a controller. The non-volatile memory is divided into a plurality of physical blocks. Each physical block is divided into a plurality of physical pages. The connection interface is connected to a host. The controller is connected to the connection interface. When the controller performs a block-reconfiguration operation, the controller re-adjusts a position in the physical blocks where data is disposed to obtain a usable physical block. Movement of one portion of the data related to the block-reconfiguration operation is performed when the controller operates an initial operation. Movement of another portion of the data related to the block-reconfiguration operation is performed when the controller processes a read command from the host.

Abstract: A load request is received to retrieve a piece of data from a location in memory and the load request follows one or more store requests in a set of instructions to store a piece of data in the location in memory. One or more possible locations in a cache for a piece of data corresponding to the location in memory is determined. Each possible location of the one or more possible locations in the cache is determined. It is then determined if at least one location of the one or more possible locations contains data to be stored in the location in memory. Data in one location of the at least one location is loaded, the data in the one location is from a store request of the one or more store requests and the store request is closest in the set of instructions to the load request.

Abstract: A method includes monitoring a number of read access requests to an address for data stored on a backing store. The method also includes comparing the number of read access requests to a read access threshold. The read access threshold includes a threshold number of read access requests for the address. The method also includes caching data corresponding to a write access request to the address in response to determining that the number of read access requests satisfies the read access threshold.

Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.

Abstract: Various embodiments for initializing metadata in a computing storage environment by a processor. A Release Generation Number (RGN) is associated with a volume, and an RGN is associated with a metadata track. Upon a release of storage space in the volume, the RGN associated with the volume is incremented. Upon an initialization of the metadata track, the RGN associated with the metadata track is updated to be consistent in generation with the RGN associated with the volume. Upon an access of the metadata track, the RGN of the metadata track is compared against the RGN of the volume, and the metadata track is initialized if a match is not found.