Abstract: Embodiments of the present invention generally relate to binary block transmission codes for high-speed network transmissions. More specifically, embodiments of the present invention relate to bounded-disparity run-length-limited forward error correction codes and methods of constructing and utilizing same. In one embodiment, a method for generating binary block bounded-disparity run-length-limited forward error correction transmission codes comprises selecting an existing base code, deriving a sub-code from the existing base code, having properties indicated by disparity bound, run-length limit and minimum distance, ascertaining a plurality of codewords and control characters from within the sub-code, encoding Messages to be transmitted with at least one codeword from the plurality of codewords, transmitting codewords from a transmitter to a receiver, and decoding the codewords into Messages.

Abstract: An error pattern analysis unit specifies positions of discarded packets in continuously transmitted groups of packets. A QoS control unit estimates the cause of a communication error based on the specified positions of discarded packets, and performs QoS control based on the estimated cause of the communication error.

Abstract: An apparatus and method for assessing image quality in real-time in consideration of both a coding error generated in an image processing process and a packet error generated in an image transmission process are provided. The apparatus for assessing image quality in real-time includes: an image quality measurement unit measuring image degradation generated in processing an image; a packet degradation detection unit detecting a packet error generated in transmitting the image; and final outcome drawing unit finally assessing the quality of the image in consideration of both a degradation degree of the image measured by the image quality measurement unit and the packet error measured by the packet degradation detection unit.

Abstract: A method and system for command queuing in disk drives may improve performance by queuing multiple commands and sequentially executing them automatically without firmware intervention. The method may use a number of queues, e.g., a staging queue for commands to be executed, an execution queue for commands currently being executed, or a holding queue for commands which may have been executed but have not received a status report from a host.

Abstract: A low density parity check (LDPC) family of codes is constructed by: determining a protograph for a mother code for the LDPC family of codes. The protograph is lifted by a lifting factor to design code specific protograph for a code. The method also includes constructing a base matrix for the code. The base matrix is constructed by replacing each zero in the code specific protograph with a ‘?1’; and replacing each one in the code specific protograph with a corresponding value from the mother matrix. The LDPC code includes a codeword size of at least 1344, a plurality of information bits, and a plurality of parity bits. The LDPC code is based on a mother code of code length 672.

Abstract: A memory system includes code data generating section which generates code data based on write data. A nonvolatile semiconductor memory stores the write data and the code data for the write data and outputs read data and the code data for the read data. An error correcting section is configured to correct an error bit included in the read data using the read data and the code data for the read data, and outputs the read data which includes the error bit in accordance with a setting. An interface section receives the write data from outside of the memory system, and outputs the read data to outside of the memory system.

Abstract: Transmitters and receivers deal with streams of data, wherein the receiver is expected to begin using received data before receiving all of the data. Concurrent streams are sent and FEC coding is used with the streams and done as an aggregate. The transmitter performs FEC operations over the plurality of streams, wherein source blocks from at least two streams logically associated into a jumbo source block and FEC processing is performed to generate one or more jumbo repair block from the jumbo source block. Each of the source blocks comprises one or more source symbols from their respective stream. The jumbo source symbols can be of constant size and are suitably aligned along size boundaries that make processing efficient. Each source symbol need not be the same size, and the number of source symbols from each stream in a jumbo source block need not be the same value across streams.

Abstract: A flash memory controller comprises a flash memory interface controller, a host interface controller, a random-access memory (RAM) interface controller, an ECC encoder, an ECC divider, an ECC constructor and an ECC decoder. The ECC encoder is configured to receive a write information datum from the host interface controller and generate an ECC datum. The ECC divider is configured to divide the generated ECC datum into a plurality of ECC segments. The ECC constructor is configured to receive a plurality of ECC segments from the flash memory interface controller and construct an ECC datum. The ECC decoder is configured to correct errors of a read information datum based on a read information datum and the constructed ECC datum and forward the corrected read information datum to the host interface controller when operated in a read mode.

Abstract: An LDPC decoder, applicable to LDPC codes including codes where check nodes within the same group are connected to a common bit node, successively processes groups of check nodes in a particular iteration, including updating bit nodes in that same iteration responsive to messages generated in response to processing a group of check nodes. Within an iteration, the LDPC decoder may also track the number of unresolved parity check equations, and cease iterating or output to an outer block decoder if that number reaches a local minima or standard minimum, falls below a predetermined threshold, or its rate of change falls below a predetermined threshold, indicating a lack of convergence or false convergence condition. The LDPC decoder may also provide a feedback assist to a demodulator. Also, a novel memory configuration may store messages generated by the decoder in the course of check node processing.

Abstract: A joint coding method in a mobile communication system is disclosed. To block-code k?-bit first data requiring a received signal quality and k2˜bit second data requiring a different received signal quality, the present invention includes configuring a first block code generation matrix meeting a first minimum hamming distance, configuring a second block code generation matrix meeting a second minimum hamming distance, and configuring a third block code generation matrix including the first block code generation matrix, the second block code generation matrix and a zero matrix of a specific size. Accordingly, the present invention encodes and transmits two data requiring different received signal qualities by one coding scheme, thereby enabling each data to have the required received signal quality in decoding.

Abstract: A method of processing a DAB audio stream, the method comprising: receiving a compressed and modulated DAB audio stream comprising a plurality of audio frames encoded with scale factors and a DAB-CRC error detection code for indicating errors in the scale factors; demodulating the DAB stream; and processing the demodulated and still compressed DAB stream responsive to the DAB-CRC of at least one audio frame of the plurality of audio frames; by determining a trend in values of scale factors and repairing or concealing the error in the scale factor responsive to the trend.

Abstract: An information processing device implements error control including at least one of error detection and error correction. The device comprises an information bit sequence acquiring unit and an encoder. The information bit sequence acquiring unit acquires an information bit sequence. The encoder generates a redundant bit sequence enabling execution of error control of the entire information bit sequence, the redundant bit sequence being generated through encoding by a predetermined code based on the information bit sequence and generates a codeword that includes the information bit sequence and the redundant bit sequence. The encoder generates the redundant bit sequence in such a way that one or more bits contained in the redundant bit sequence each functions as a parity bit for one of a plurality of divided information bit sequences produced by dividing the information bit sequence.

Abstract: Circuits, architectures, methods and algorithms for joint channel-code decoding of linear block codes, and more particularly, for identifying and correcting one or more errors in a code word and/or for encoding CRC (or parity) information. In one aspect, the invention focuses on use of (i) remainders, syndromes or other polynomials and (ii) Gaussian elimination to determine and correct errors. Although this approach may be suboptimal, the present error checking and/or detection scheme involves simpler computations and/or manipulations than conventional schemes, and is generally easier to implement logically.

Abstract: A method of testing a semiconductor memory device includes reading previously written test data from the semiconductor memory device simultaneously through at least two data I/O connections, e.g., pins or pads, of the semiconductor memory device. The signals from the two data I/O connections are combined to produce a compound output signal. The compound output signal is received by a single I/O channel of a tester. The tester compares the compound output signal to a predetermined voltage level, and determines whether the semiconductor memory device is operating properly based on the comparison of the compound output signal to the predetermined voltage level.

Abstract: A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream.

Abstract: Systems and methods are provided for correcting absorb sets and near absorb sets in the (2048, 1723) LDPC code used in 10 GBase-T transmission systems. Absorb sets and near absorb sets correspond to error patterns that, due to the structure and imperfections of the LDPC code, cannot easily be corrected using standard correction methods. To correct these error patterns, a set of failed syndrome checks associated with the error pattern can be identified, and the 4, 8, 12, or 16 error patterns associated with the failed syndrome checks can be determined. The codeword may then be corrected based on the error pattern that most likely occurred.

Abstract: A method and apparatus for Turbo encoding uses a set of rate-compatible Turbo Codes optimized at high code rates and derived from a universal constituent code. The Turbo Codes have rate-compatible puncturing patterns. The method comprises: encoding a signal at a first and second encoder using a best rate 1/2 constituent code universal with higher code rates, the first encoder and the second encoder each producing a respective plurality of parity bits for each information bit; puncturing the respective plurality of parity bits at each encoder with a higher rate best puncturing patterns; and puncturing the respective plurality of parity bits at each encoder with a lower rate best puncturing pattern. In a variation, the best rate 1/2 constituent code represents a concatenation of polynomials 1+D2+D3 (octal 13) and 1+D+D3 (octal 15), D a data bit. A Turbo Encoder is provided which has hardware to implement the method.

Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register.

Abstract: A system and a method detects errors when writing data to a memory in a computer system. An error detection memory write request for writing an error detection value to a memory location within the memory section is issued, the error detection value being associated with the block of data. A data memory write request for writing the block of data to the memory section is issued such that at least part of the block of data is written to the memory location. A check is performed to determine whether the error detection value in the error detection memory write request corresponds to the block of data in the data memory write request.

Abstract: FEC (Forward Error Correction) decoder with dynamic parameters. A novel means by which FEC parameters may be encoded into, and subsequently extracted from, a signal stream to allow for adaptive changing of any 1 or more operational parameters that govern communications across a communication channel. FEC parameters are encoded directly into a data frame such that the data frame is treated identical to all other data frames within the signal stream. When the data frame actually includes FEC parameters, it is characterized as a CP (Control Packet) type. For example, when decoding an MPEG stream, an MPEG block that includes FEC parameters, that MPEG block is characterized as a CP MPEG block. The means by which FEC parameters are encoded and extracted from the signal stream allows for much easier adaptive modification of the manner by which signal are encoded, modulated, and processed within a communication system.