Patents Examined by Stephen Rosasco
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Patent number: 9846358Abstract: A photomask includes a light transmission substrate, and a transfer pattern disposed over the light transmission substrate, a shape of the transfer pattern being transferred onto a wafer by an exposure process. The transfer pattern comprises a first transfer pattern having a closed loop shape and having a first thickness, and a plurality of second transfer patterns disposed in an opening surrounded by the first transfer pattern, the plurality of second transfer patterns being arrayed in a first direction such that adjacent second transfer patterns are spaced apart from each other by a first distance, the second transfer patterns having a second thickness which is less than the first thickness of the first transfer pattern.Type: GrantFiled: November 4, 2015Date of Patent: December 19, 2017Assignee: SK HYNIX INC.Inventor: Tae Joong Ha
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Patent number: 9841667Abstract: A reflective photomask includes a substrate and a reflective layer on the substrate. The reflective layer has a top surface opposite to the substrate and a reflectivity distribution on the top surface. The reflective layer includes mask patterns, the mask patterns having sizes depending on the reflectivity distribution. The mask patterns include a first pattern and a second pattern, the first pattern having a first space size smaller than a second space size of the second pattern. The first pattern is provided in a first region of the top surface, and the second pattern is provided in a second region of the top surface, wherein a reflectivity in the first region is lower than a reflectivity in the second region.Type: GrantFiled: September 3, 2015Date of Patent: December 12, 2017Assignee: Toshiba Memory CorporationInventor: Takashi Kamo
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Patent number: 9817308Abstract: There is provided a pellicle wherein the pellicle frame is formed with a protrusion which extends either inward or outward from the pellicle frame so that an air passage (vent hole) can extend in it to turn upward or downward to open in the atmosphere or in the pellicle closed space (the space interior to the pellicle frame) so that it is possible to secure a wider opening area for filtration to enable prompt air ventilation whereby the pellicle membrane does not undergo extreme inflation or deflation and thus the pellicle membrane is protected from damages.Type: GrantFiled: February 18, 2016Date of Patent: November 14, 2017Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventor: Toru Shirasaki
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Patent number: 9817307Abstract: Any defects in the reflective multilayer coating or absorber layer of an EUV mask are problematic in transferring a pattern of the EUV mask to a wafer since they produce errors in integrated circuit patterns on the wafer. In this regard, a method of manufacturing an EUV mask is provided according to various embodiments of the present disclosure. To repair the defect, a columnar reflector, which acts as a Bragg reflector, is deposited according to various embodiments so as to locally compensate and repair the defect. According to the embodiments of the present disclosure, the reflective loss due to the defect can be compensated and recover the phase different due to the defect from, so as to form a desirable wafer printed image.Type: GrantFiled: January 29, 2016Date of Patent: November 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao Yu, Ming-Yun Chen
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Patent number: 9817318Abstract: According to an embodiment, mask manufacturing equipment includes a detector, an irradiator, a calculator, and a controller. The detector detects positional deviation of a pattern formed on a mask substrate. The irradiator irradiates the mask substrate with laser light to form a heterogeneous layer that is expanded in volume in the mask substrate. The calculator calculates an area periphery irradiation condition under which the irradiator is caused to emit laser light to a peripheral area of the pattern on the basis of the positional deviation detected by the detector so that the pattern area is reduced by forming the heterogeneous layer in the peripheral area of the pattern. The controller controls the irradiator to form the heterogeneous layer in the peripheral area of the pattern according to the area periphery irradiation condition.Type: GrantFiled: March 12, 2015Date of Patent: November 14, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tetsuya Kugimiya, Kazuya Fukuhara, Hidenori Sato
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Patent number: 9810978Abstract: A EUV mask comprises a low thermal expansion material (LTEM) substrate, a reflective multi-layer (ML) over the LTEM substrate, and a patterned absorber layer over the reflective ML. The reflective ML includes a defect. The EUV mask further comprises a mark associated with the defect. The mark is one of: a deposit over the patterned absorber layer at a distance offset from the defect, and a cavity into the patterned absorber layer in an area over the defect.Type: GrantFiled: February 29, 2016Date of Patent: November 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsun-Chuan Shih, Yuan-Chih Chu
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Reticle with reduced transmission regions for detecting a defocus condition in a lithography process
Patent number: 9810916Abstract: A reticle for a semiconductor lithography process includes a glass plate having regions with a reduced optical transmission factor. The regions may include arrays of elements comprising defects such as cracks or voids which are formed by laser pulses. The regions may be adjacent to openings in an opaque material at the bottom of the reticle to shield the openings from a portion of the light which illuminates the reticle from the top. As a result, the light which exits the reticle and is used to pattern a substrate has an asymmetric intensity. This allows the substrate to be patterned with an inspection mark which indicates whether a defocus condition exists, and whether there is a positive or negative defocus condition. Related methods use a reticle to form a pattern on a substrate and for adjusting a focus condition using a reticle.Type: GrantFiled: October 13, 2015Date of Patent: November 7, 2017Assignee: SanDisk Technologies LLCInventor: Akihiro Tobioka -
Patent number: 9798244Abstract: Methods, apparatus, and system for minimizing defectivity in top-coat-free immersion photolithography are provided. Embodiments include forming a photomask by defining a first pattern including a main functional pattern in the photomask; and defining a second pattern including a sub-resolution fill pattern in the photomask in areas between or and/or within structures of the first pattern, the fill pattern having a pitch or range of pitches smaller than a minimum resolved pitch of the lithographic exposure and/or at least a part of the sub-resolution structures of the sub-resolution fill pattern not substantially modifying an imaging of any structure of the main functional pattern in the lithographic exposure.Type: GrantFiled: November 17, 2015Date of Patent: October 24, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Arthur Hotzel, Philipp Jaschinsky, Remi Riviere, Wolfram Grundke
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Patent number: 9791774Abstract: The present disclosure relates to a method for forming a nanostencil mask. The method involves irradiating a substrate to increase resistivity of a plurality of first portions of the substrate relative to one or more second portions of the substrate surrounding the plurality of first portions. The method also involves passing a current through the substrate, the current preferentially passing through and weakening the one or more second portions of the substrate. This preference is a result of the higher resistivity in the one or more first portions of the substrate causing the current to pass through the relatively lower resistivity second portion(s). The method also involves subjecting the substrate to a material removal process, the material removal process preferentially removing the weakened one or more second portions of the substrate and thereby forming a nanostencil mask comprising the plurality of first portions of the substrate.Type: GrantFiled: April 15, 2015Date of Patent: October 17, 2017Assignee: NATIONAL UNIVERSITY OF SINGAPOREInventors: Mark Brian Howell Breese, Sara Azimi
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Patent number: 9778559Abstract: A halftone phase shift film containing Si and N and/or O is deposited on a transparent substrate by reactive sputtering of a Si-containing target with a reactive gas containing N and/or O. One layer is sputter deposited while the reactive gas flow rate is set equal to or lower than the lower limit of the reactive gas flow rate in the hysteresis region, and another layer is sputter deposited while the reactive gas flow rate is set inside the lower and upper limits of the reactive gas flow rate in the hysteresis region. The phase shift film exhibits satisfactory in-plane uniformity of optical properties.Type: GrantFiled: March 23, 2016Date of Patent: October 3, 2017Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Takuro Kosaka, Yukio Inazuki
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Patent number: 9778558Abstract: A mask for photolithography includes: a transparent substrate; a phase shift pattern on the transparent substrate and configured to change a phase of light; a dielectric layer on the transparent substrate; and a negative refractive-index meta material layer on the dielectric layer.Type: GrantFiled: June 26, 2015Date of Patent: October 3, 2017Assignees: Samsung Display Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Yong Son, Min Kang, Bong-Yeon Kim, Hyun-Joo Lee, Hyang-Shik Kong, Jin-Ho Ju, Kyoung-Sik Kim, Seung-Hwa Baek
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Patent number: 9778560Abstract: A halftone phase shift film containing Si and N and/or O is deposited on a transparent substrate by reactive sputtering using a silicon-containing target with a reactive gas. Different powers are applied across a plurality of targets so that two different sputtering modes selected from metal, transition and reaction modes associated with a hysteresis curve are applied to the targets. The phase shift film exhibits satisfactory in-plane uniformity of optical properties.Type: GrantFiled: March 23, 2016Date of Patent: October 3, 2017Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventor: Takuro Kosaka
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Patent number: 9766538Abstract: A pellicle frame and a pellicle made with it is proposed in which at least one pair of the side bars of the frame are made to have a deflection (bow) which has an amount or a distance of displacement measured at the middle point of the side bar accounting for 0.01 through 1% of the length of the respective side bar.Type: GrantFiled: November 16, 2015Date of Patent: September 19, 2017Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventor: Kazutoshi Sekihara
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Patent number: 9766536Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.Type: GrantFiled: July 17, 2015Date of Patent: September 19, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
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Patent number: 9766540Abstract: A photomask and a method of forming the same, the photomask including a transparent substrate; a light shielding pattern on the transparent substrate, the light shielding pattern including molybdenum and silicon; and an etch stop layer covering at least a sidewall of the light shielding pattern, wherein the etch stop layer has an etch rate lower than an etch rate of the light shielding pattern with respect to an ammonia-based cleaning solution.Type: GrantFiled: December 22, 2015Date of Patent: September 19, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Keun Oh, Hyungho Ko, Inkyun Shin, Jaehyuck Choi, JunYoul Choi
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Patent number: 9759997Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane with a thermal conductive surface; a porous pellicle frame; and a thermal conductive adhesive layer that secures the pellicle membrane to the porous pellicle frame. The porous pellicle frame includes a plurality of pore channels continuously extending from an exterior surface of the porous pellicle frame to an interior surface of the porous pellicle frame.Type: GrantFiled: December 17, 2015Date of Patent: September 12, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Amö Chen, Yun-Yue Lin, Ta-Cheng Lien, Hsin-Chang Lee, Chih-Cheng Lin, Jeng-Horng Chen
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Patent number: 9754794Abstract: Techniques related to semiconductor fabrication are generally described herein. An example fabrication method may include coupling, by a lithographic equipment, a surface of a planar waveguide structure with a first surface of a photolithographic mask. Some example methods may also include directing, by the lithographic equipment, a lithography light beam into the planar waveguide structure, causing a surface plasmon being emitted from the surface of the planar waveguide structure when the lithography light beam is reflected by internal surfaces of the planar waveguide structure, effectuating an attenuated total reflection. Some example methods may further include directing, by the lithographic equipment, an evanescent wave caused by the surface plasmon through the photolithographic mask, wherein the evanescent wave has a sub-diffraction characteristic and is used as a photolithographic light source.Type: GrantFiled: September 3, 2012Date of Patent: September 5, 2017Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventor: Qingkang Wang
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Patent number: 9748107Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.Type: GrantFiled: October 23, 2015Date of Patent: August 29, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Chun Lo, Min-Hung Cheng, Hsiao-Wei Su, Jeng-Shiun Ho, Ching-Che Tsai, Cheng-Cheng Kuo, Hua-Tai Lin, Chia-Chu Liu, Kuei-Shun Chen
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Patent number: 9746763Abstract: Provided is a phase shift mask including a substrate, a phase shift layer, and a shielding layer. The phase shift layer is located on the substrate. A pattern of the phase shift layer includes a main pattern and sub-resolution assist features (SRAFs). The SRAFs are disposed around the main pattern. The phase shift layer has a transmission, and the transmission is larger than 6%. The shielding layer at least covers the SRAFs of the phase shift layer.Type: GrantFiled: August 4, 2015Date of Patent: August 29, 2017Assignee: Winbond Electronics Corp.Inventor: Kao-Tun Chen
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Patent number: 9746762Abstract: Provided is a conductive film coated substrate, including a conductive film formed thereon. In a relationship between a bearing area (%) and a bearing depth (nm) that are obtained by measuring, with an atomic force microscope, a region of 1 ?m×1 ?m of a surface of the conductive film, the surface of the conductive film satisfies a relationship that (BA70?BA30)/(BD70?BD30) is 15 or more and 260 or less (%/nm), and a maximum height (Rmax) is 1.3 nm or more and 15 nm or less.Type: GrantFiled: September 22, 2014Date of Patent: August 29, 2017Assignee: HOYA CORPORATIONInventors: Kazuhiro Hamamoto, Yoichi Usui