Abstract: A display device includes a display panel, a circuit board, a first conductive film, first and second lower films, and first and second adhesive layers. The display panel includes a display area and a pad area which includes a first pad part. The circuit board is attached on the display panel and includes a lead part overlapping the first pad part. The first conductive film is between the display panel and the circuit board and electrically connects the first pad part and the lead part to each other. The first and second lower films are attached to the display panel to respectively correspond to the display area and the pad area. A thickness of the second adhesive layer between the display panel and the second lower film is less than a thickness of the first adhesive layer between the display panel and the first lower film.

Abstract: A display device includes a substrate that includes a display area and a pad area, and a plurality of data pads that are provided on the pad area of the substrate and arranged along a first direction and a second direction, where the plurality of data pads includes a first data pad, a second data pad that is disposed adjacent to the first data pad along the first direction, a third data pad that is disposed adjacent to the first data pad along the second direction, and a fourth data pad that is disposed adjacent to the second data pad along the second direction, and the first data pad and the second connection wire are respectively disposed in different layers.

Abstract: A device includes a buried oxide layer disposed on a substrate, a first region disposed on the buried oxide layer and a first ring region disposed in the first region. The first ring region includes a portion of a guardring. The device further includes a first terminal region disposed in the first ring region, a second ring region disposed in the first region and a second terminal region disposed in the second ring region. The first terminal region is connected to an anode and the second terminal region is connected to a cathode. The first region has a graded doping concentration. The first region, the second ring region and the second terminal region have a first conductivity type, and the first ring region and the first terminal region have a second conductivity type. The first conductivity type is different from the second conductivity type.

Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the recess, a first conductive layer disposed on a front side of the circuit substrate, and a second conductive layer disposed on an inner wall of the recess. The first conductive layer extends into the through holes and the second conductive layer extends into the through holes and coupled to the first conductive layer.

Abstract: A memory array includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.

Abstract: A method of forming a semiconductor device includes forming a dummy gate over a substrate, forming dielectric materials over a top surface and sidewalls of the dummy gate, and replacing the dummy gate with a gate structure. The dummy gate has a first width located a first distance away from the substrate, a second width located a second distance away from the substrate, and a third width located a third distance away from the substrate. The second distance is less than the first distance. The second width is less than the first width. The third distance is less than the second distance. The third width is greater than the second width.

Abstract: A semiconductor structure includes a substrate, a plurality of micro semiconductor devices and a fixing structure. The micro semiconductor devices are disposed on the substrate. The fixing structure is disposed between the substrate and the micro semiconductor devices. The fixing structure includes a plurality of conductive layers and a plurality of supporting layers. The conductive layers are disposed on the lower surfaces of the micro semiconductor devices. The supporting layers are connected to the conductive layers and the substrate. The material of each of the conductive layers is different from the material of each of the supporting layers.

Abstract: A method for producing a plurality of radiation emitting semiconductor devices and a radiation emitting semiconductor device are disclosed. In an embodiment a method include providing an auxiliary carrier, applying a plurality of radiation-emitting semiconductor chips to the auxiliary carrier with front sides so that rear sides of the semiconductor chips are freely accessible, wherein each rear side of the respective semiconductor chip has at least one electrical contact, applying spacers to the auxiliary carrier so that the spacers directly adjoin side surfaces of the semiconductor chips and applying a casting compound between the semiconductor chips by a screen printing process such that a semiconductor chip assembly is formed, wherein a screen for the screen printing process has a plurality of cover elements, and wherein each cover element covers at least one electrical contact.

Abstract: A semiconductor device includes a metal plate; a sidewall member surrounding a periphery of a space above the metal plate; a circuit board provided on the metal plate; a semiconductor chip provided on the circuit board; a first wire connecting the semiconductor chip and an interconnect part of the circuit board; a first resin member covering a bonding portion between the semiconductor chip and the first wire; and a second resin member provided in the space, the second resin member covering an upper surface of the metal plate, the circuit board, the first resin member, and the first wire. A Young's modulus of the first resin member is greater than a Young's modulus of the second resin member. A volume of the second resin member is greater than a volume of the first resin member.

Abstract: Provided is a display device including an organic insulating layer; a pixel electrode on the organic insulating layer; a pixel defining layer configured to cover an edge of the pixel electrode, having an opening corresponding to the pixel electrode, the pixel defining layer including a first layer including an inorganic insulating material and a second layer having less light transmittance in a first wavelength band than the first layer; an intermediate layer on a portion of the pixel electrode exposed via the opening, and including an emission layer; and an opposite electrode on the intermediate layer.

Abstract: The present disclosure concerns a mounting device for semiconductor packages, and a heat dissipation assembly with such a mounting device. The mounting device includes a bottom side comprising one or more cavities to house semiconductor packages, and a top side comprising a plurality of holes extending from the bottom side to the top side for accommodating contact pins of the semiconductor packages. A fixation mechanism fixes the mounting device to a heat dissipation structure.

Abstract: A semiconductor device includes a substrate, an electrical conductor and a passivation layer. The substrate includes a first surface. The electric conductor is over the first surface of the substrate. The passivation layer is over the first surface of the substrate. The passivation layer includes a first part and a second part. In some embodiments, the first part is in contact with an edge of the electrical conductor, the second part is connected to the first part and apart from the edge of the electrical conductor, and the first part of the passivation layer has curved surface.

Abstract: An imaging device including: a semiconductor substrate having a first and second surface opposite to the first surface; a microlens located closer to the first surface than the second surface; a first photoelectric converter located between the first surface and the microlens, where the first photoelectric converter includes a first electrode, a second electrode, and a photoelectric conversion layer that is located between the first electrode and the second electrode and that converts light into electric charges; and a signal detecting section located in the semiconductor substrate, the signal detecting section being configured to output a signal corresponding to the electric charges. The first photoelectric converter is the closest of any photoelectric converter existing between the first surface and the microlens to the first surface, and a focal point of the microlens is located below a lowermost surface of the photoelectric conversion layer and above the signal detecting section.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate, an insulating layer, a first crack stopper, and a first crack detection line. The base substrate includes a display region and a non-display region. The insulating layer is located on the base substrate. The first crack stopper is located in the non-display region and is configured to block the first crack in the insulating layer from extending towards the display region. The first crack detection line is located in the non-display region, an edge of the orthographic projection of the first crack stopper on the base substrate close to the display region is a blocking edge, and the orthographic projection of the first crack detection line on the base substrate is located at a side of the orthographic projection of the first crack stopper on the base substrate away from the blocking edge.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a substrate comprising a storage region, forming stacked gates of storage transistors on the substrate; forming side walls on two sides of each stacked gate wherein the top surfaces of side walls are arranged to be lower than the top surfaces of the stacked gates; performing ion implantation in the storage region defined by the side walls; and performing an ashing process and a wet cleaning process using the side walls as protective layers of the stacked gates to remove a photoresist remaining after the ion implantation. The present disclosure further provides a semiconductor device formed according to the manufacturing method. According to the semiconductor device and the manufacturing method thereof, the problem of stacked gate collapse from the ion implantation process can be solved, thereby improving the yield.

Abstract: A light emitting device is provided. The light emitting device includes a light emitting assembly having a first light emitting diode package structure and a second light emitting diode package structure. The light emitting assembly can generate a mixed light source having a spectral deviation index. The first light emitting diode package structure can generate a first light source having a first spectral deviation index. The second light emitting diode package structure can generate a second light source having a second spectral deviation index. When the first light source and the second light source are within a range from 460 to 500 nm, a sum of the first spectral deviation index and the second spectral deviation index is within a range from ?0.3 to 0.3, and a difference between the first spectral deviation index and the second spectral deviation index is at least greater than 0.2.

Abstract: An embodiment includes a semiconductor device including a semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first insulation layer disposed on the semiconductor structure; a first electrode disposed on the first conductive semiconductor layer; a second electrode disposed on the second conductive semiconductor layer; a first cover electrode disposed on the first electrode; a second cover electrode disposed on the second electrode; and a second insulation layer extending from an upper surface of the first cover electrode to an upper surface of the second cover electrode.

Abstract: An electronic device, a lead frame, and a method, including providing a lead frame with a Y-shaped feature having branch portions connected to a dam bar in a prospective gap in an equally spaced repeating lead pitch pattern, and a set of first leads extending parallel to one another along a first direction and spaced apart from one another along a second direction in lead locations of the repeating lead pitch pattern, attaching a semiconductor die to a die attach pad of the lead frame, attaching bond wires between bond pads of the semiconductor die, and the first leads, enclosing first portions of the first leads, the die attach pad, and a portion of the semiconductor die in a package structure, and performing a dam bar cut process that cuts through portions of the dam bar between the lead locations of the repeating lead pitch pattern.

Abstract: A semiconductor structure, a method for producing a semiconductor structure and a light emitting device are disclosed. In an embodiment a semiconductor structure includes a plurality of discrete encapsulated semiconductor nanoparticles and a plurality of discrete semiconductor free nanoparticles, wherein the discrete encapsulated semiconductor nanoparticles and the discrete semiconductor free nanoparticles form an agglomerate.

Abstract: The present application provides a display substrate having a plurality of subpixel areas. The display substrate includes a base substrate; a first electrode layer on the base substrate and including a plurality of first electrodes respectively in the plurality of subpixel areas; an auxiliary electrode layer; and an insulating layer between the first electrode layer and the auxiliary electrode layer. The first electrode layer and the auxiliary electrode layer are spaced apart and insulated from each other by the insulating layer. An orthographic projection of each individual one of the plurality of first electrodes on the base substrate at least partially overlap with an orthographic projection of the auxiliary electrode layer on the base substrate. Each of the plurality of first electrodes is electrically connected to a pixel circuit configured to drive light emission in a respective one of the plurality of subpixel areas.