Abstract: A method of fabricating an electronic device including a semiconductor memory includes forming a first conductive structure extending in a first direction and having a closed-loop shape, forming a second conductive structure extending in a second direction and having a closed-loop shape, the second direction intersecting the first direction, forming a memory cell located at an intersection of the first conductive structure and the second conductive structure, forming first conductive patterns extending in the first direction by etching an end portion of the first conductive structure, forming second conductive patterns extending in the second direction by etching an end portion of the second conductive structure, forming a first protective layer on an etched surface of each of the first conductive patterns and the second conductive patterns, and forming a gap-fill layer on the first protective layer.

Abstract: Example embodiments relate to selective deposition for interdigitated patterns in solar cells. One embodiment includes a method for creating an interdigitated pattern for a solar cell. The method includes providing a substrate of the solar cell. A surface of the substrate includes one or more exposed regions and one or more regions covered by a patterned first passivation layer stack protected by a hard mask. The method also includes selectively depositing a second passivation layer stack that includes at least a first layer of amorphous silicon (a-Si) on the one or more exposed regions such that the first passivation layer stack and the second passivation layer stack form the interdigitated pattern. Selectively depositing the second passivation layer stack includes adding a sublayer of the first layer on the hard mask, etching the added sublayer on the hard mask, and cleaning a surface of the remaining added sublayer.

Abstract: A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.

Abstract: A transistor including a substrate, a source, a drain, an active portion, a fin-shaped gate, and an insulation layer is provided. The source is located on the substrate. The drain is located on the substrate. The active portion connects the source and the drain. The fin-shaped gate wraps the active portion. A first portion of the insulation layer separates the fin-shaped gate from the active portion, a second portion of the insulation layer separates the fin-shaped gate from the substrate, a third portion of the insulation layer separates the fin-shaped gate from the source and from the drain, and a fourth portion of the insulation layer is located on a surface of the fin-shaped gate facing away from the active portion. Here, the insulation layer is integrally formed.

Abstract: A method for fabricating an electrically isolated diamond nanowire includes forming a diamond nanowire on a diamond substrate, depositing a dielectric or a polymer on the diamond nanowire and on the diamond substrate, planarizing the dielectric or the polymer, etching a portion of the planarized dielectric or polymer to expose a first portion of the diamond nanowire, depositing a metal layer to conformably cover the first portion of the diamond nanowire, and implanting ions into a second portion of the diamond nanowire between the first portion of the diamond nanowire and the diamond substrate or at an intersection of the diamond nanowire and the diamond substrate, wherein the ions are implanted at an oblique angle from a first side of the diamond nanowire.

Abstract: A method includes dispensing a liquid etchant onto a wafer, wherein the wafer is free from rotation during dispensing the liquid etchant; blowing the liquid etchant on the wafer using a gas flow, wherein a direction of the gas flow remains substantially constant during dispensing the liquid etchant; and turning the gas flow off after a target structure on the wafer is etched away by the liquid etchant.

Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.

Abstract: A synthetic antiferromagnetic structure for a spintronic device is disclosed and has an FL2/Co or Co alloy/antiferromagnetic coupling/Co or Co alloy/CoFeB configuration where FL2 is a ferromagnetic free layer with intrinsic PMA. Antiferromagnetic coupling is improved by inserting a Co or Co alloy dusting layer on top and bottom surfaces of the antiferromagnetic coupling layer. The FL2 layer may be a L10 ordered alloy, a rare earth-transition metal alloy, or an (A1/A2)n laminate where A1 is one of Co, CoFe, or an alloy thereof, and A2 is one of Pt, Pd, Rh, Ru, Ir, Mg, Mo, Os, Si, V, Ni, NiCo, and NiFe, or A1 is Fe and A2 is V. A method is also provided for forming the synthetic antiferromagnetic structure.

Abstract: The present disclosure provides a method for fabricating a magnetic semiconductor device, including receiving a semiconductor wafer, disposing the semiconductor wafer under a first electromagnetic element, wherein the first electromagnetic element comprises a primary dimension and a secondary dimension from a top view perspective, the primary dimension being greater than the secondary dimension, and displacing the semiconductor wafer along a predetermined path along the secondary dimension of the first electromagnetic element.

Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.

Abstract: The present application discloses a display panel and a display apparatus. The display panel includes a substrate, and a plurality of first-layer conducting wires, where each of the first-layer conducting wires is disposed on the substrate, a polarizing color filter layer is disposed on the first-layer conducting wire and forms a color filter film with anisotropy, and the first-layer conducting wire is connected to a column data driver and a pixel driver of the display panel.

Abstract: A flexible display apparatus including a protective film is provided. The protective film can include penetrating holes extending in parallel in a direction perpendicular to a bending direction. Deformation preventing elements having the modulus of elasticity higher than the protective film can be disposed in the penetrating holes of the protective film. The protective film and the deformation preventing elements can be coupled with a device substrate including a light-emitting device, an encapsulating layer and a barrier layer, which are sequentially stacked on the device substrate by an adhesive layer. The adhesive layer can include a first adhesive element overlapping with the protective film, and second adhesive elements overlapping with the deformation preventing elements. The second adhesive elements can have the modulus of elasticity lower than the first adhesive element. Thus, in the flexible display apparatus, the deformation of the protective film due to a bending stress can be prevented.

Abstract: An infrared sensor substrate includes: column signal lines; row signal lines; a pixel array of pixels including infrared detector elements connected to the column signal lines and the row signal lines. The infrared sensor substrate includes: a current source connected to the infrared detector elements via the column signal lines; a voltage source that applies a voltage to the infrared detector elements via the row signal lines; output terminals connected to the column signal lines, the output terminals being connectable to a signal processing circuit substrate that processes output signals of the infrared detector elements. The infrared sensor substrate includes a monitoring terminal capable of monitoring the voltage applied to the infrared detector elements by the first voltage source.

Abstract: Provided is a method of detecting photoresist scums and photoresist residues. A carrier is provided. The carrier has a photoresist layer with opening patterns therein. A plasma etching process is performed to the opening patterns of the photoresist layer. Charges are injected to the opening patterns of the photoresist layer. Whether a photoresist scum or residue is present in at least one of the opening patterns is detected.

Abstract: A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.

Abstract: A method of manufacturing a covering member includes: providing a first light-reflective member comprising a through-hole, the through-hole having first and second openings; arranging a light-transmissive resin containing a wavelength-conversion material within the through-hole; distributing the wavelength-conversion material predominantly on a side of the first opening of the through-hole within the light-transmissive resin; and after the step of distributing the wavelength-conversion material, removing a portion of the light-transmissive resin from a side of the second opening of the through-hole.

Abstract: A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.

Abstract: A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.

Abstract: The present disclosure relates to a method of forming an integrated circuit (IC). In some embodiments, a substrate is provided comprising a memory region and a logic region disposed adjacent to the memory region. The memory region comprises a non-volatile memory (NVM) device having a control gate electrode and a select gate electrode disposed between two neighboring source/drain regions over a substrate. The control gate electrode and the select gate electrode comprise polysilicon. The logic region comprises a logic device including a metal gate electrode disposed between two neighboring source/drain regions over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer.

Abstract: A multi-view display device displays a first image, a second image, and a third image generated using the arrangement structure of subpixels and color filters, the gaps between the subpixels, and the arrangement structure of black matrices. The first to third red subpixels of the first to third subpixel groups display a red portion of the first to third images, the first to third green subpixels of the first to third subpixel groups display a green portion of the first to third images, and the first to third blue subpixels of the first to third subpixel groups display a blue portion of the first to third images.