Abstract: The present application provides external bone fixation systems. The systems include one or more pairs of bone fixation platforms in the form of rings or partial rings. The platforms may be coupled to corresponding bone segments. The pair of platforms are configured to accept a plurality of struts extending therebetween. The struts are configured to attach to the platforms via joints that provide three degrees of rotation. The struts are also configured such that their longitudinal length extending between the joints/platforms can be incrementally adjusted while attached to the platforms. The struts are further configured such that their total range of length adjustment can be increased by coupling at least one add-on component to the struts in situ. The lengths of each of the plurality of struts may be adjusted to arrange the platforms, and thereby the bone segment coupled thereto, in particular relative positions and orientations.

Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate, forming at least one precursor semiconductor fin from the semiconductor substrate, etching through at least a portion of the at least one precursor semiconductor fin to form at least one patterned precursor semiconductor fin having a gap therein. The at least one patterned precursor semiconductor fin includes a first vertical surface and a second vertical surface with the gap therebetween. In addition, the method further includes forming a semiconductor material in the gap of the at least one patterned precursor semiconductor fin, in which the first vertical surface and the second vertical surface laterally surround the semiconductor material, and transforming the at least one patterned precursor semiconductor fin into at least one semiconductor fin including the semiconductor material therein.

Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.

Abstract: In accordance with some embodiments, conductive material is removed from over a first plurality of fins and second plurality of fins, wherein the first plurality of fins is located within a small gate length region and the second plurality of fins is located in a large gate length region. The removal is performed by initially performed a dry etch with a low pressure and a high flow rate of at least one etchant, which causes the conductive material to have a larger thickness over the second plurality of fins than over the first plurality of fins. As such, when a wet etch is utilized to remove a remainder of the conductive material, dielectric material between the second plurality of fins and the conductive material is not damaged.

Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate, forming at least one precursor semiconductor fin from the semiconductor substrate, etching through at least a portion of the at least one precursor semiconductor fin to form at least one patterned precursor semiconductor fin having a gap therein. The at least one patterned precursor semiconductor fin includes a first vertical surface and a second vertical surface with the gap therebetween. In addition, the method further includes forming a semiconductor material in the gap of the at least one patterned precursor semiconductor fin, in which the first vertical surface and the second vertical surface laterally surround the semiconductor material, and transforming the at least one patterned precursor semiconductor fin into at least one semiconductor fin including the semiconductor material therein.

Abstract: An apparatus and method for determining an angle ? an estimate of a true angle ? from a resolver excitation signal Vex(t)=A sin(?t) and modulated resolver output signals Vs(t,?)=A×sin(?)×sin(?t) and VC(t,?)=A×cos(?)×sin(?t), where ? is an angular frequency and t is time, is provided. The apparatus may include a converter comprising a closed loop phase-locked loop (PLL) system configured to produce an angle ? and two digital signals BitØ(?) and Bit1(?) for estimating the true angle ? using Vex(t), Vs(t,?) and VC(t,?) signals.

Abstract: A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a series of steps including: forming a transistor having source/drain regions within a fin structure and adjacent to a gate structure across over the fin structure; forming first source/drain contacts right above and electrically connected to the source/drain regions; depositing a composite barrier structure over the transistor and the first source/drain contacts; and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method further includes depositing a second etch-stop layer before depositing the composite barrier structure and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method also includes forming contacts over and electrically connected to the second source/drain contacts.

Abstract: Methods and systems for estimating properties of earth formations including conveying a carrier through a borehole having a transmitter, a first receiver, and a second receiver, the first receiver positioned a first distance from the transmitter and the second receiver positioned a second distance therefrom, generating with the transmitter a transient electromagnetic field, receiving a first measured signal at the first receiver, receiving a second measured signal at the second receiver, obtaining a total signal from the first measured signal and the second measured signal, determining a bucking coefficient, performing a bucking calculation employing the bucking coefficient, the first measured signal, and the second measured signal to extract a pipe signal, suppressing the pipe signal from the total signal to obtain a formation signal, estimating a formation property from the formation signal, and adjusting a drilling operation based on the estimated property of the formation.

Abstract: The present disclosure provides systems, apparatuses, and methods for fluid analysis. Embodiments include a removable and replaceable sampling system and an analytical system connected to the sampling system. A fluid may be routed through the sampling system and real-time data may be collected from the fluid via the sampling system. The sampling system may process and transmit the real-time data to the analytical system. The analytical system may include a command and control system that may receive and store the real-time data in a database and compare the real-time data to existing data for the fluid in the database to identify conditions in the fluid.

Abstract: A non-volatile memory including a substrate, a charge storage structure, two metal gate structures, a first dielectric layer, a second dielectric layer, a first doped region and a second doped region is provided. The charge storage structure is disposed on the substrate. The metal gate structures are disposed on the substrate at two sides of the charge storage structure. The first dielectric layer is disposed between the charge storage structure and the metal gate structures. The second dielectric layer is disposed between the charge storage structure and the substrate. The first doped region and the second doped region are disposed in the substrate at sides of the metal gate structures away from the charge storage structure.

Abstract: According to one aspect, a system configured to provide equivalent measurement values is provided. The measurement equivalency component is configured to receive, from a component, data requesting at least one measurement value meeting at least one criterion, the at least one measurement value having at least one first measurement type, determine that the at least one measurement value is not stored within at least one memory, determine that at least one stored measurement value meeting the at least one criterion and having at least one second measurement type different from the at least one first measurement type is stored within the at least one memory, and provide data descriptive of at least one equivalent measurement value based on the at least one stored measurement value to the component in response to receipt of the data requesting the at least one measurement value.

Abstract: A method for determining if an individual integrated circuit was manufactured using an individual instance of tooling includes collecting from the individual integrated circuit first data representing at least one attribute that varies as a function of the tooling used to manufacture the individual integrated circuit and second data identifying the integrated circuit as having been manufactured using the individual instance of tooling. The first data is compared to a signature of the individual instance of tooling identified by the second data. The signature is derived from the at least one attribute measured from a population of integrated circuits that were manufactured using the individual instance of tooling. The individual integrated circuit is identified as having been manufactured using the individual instance of tooling identified in the second data collected from the individual integrated circuit if the first data correlates to the signature by a predetermined threshold.

Abstract: Disclosed are a light emitting device package and a lighting apparatus. The light emitting device package includes a substrate, a light emitting structure disposed under the substrate and including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, a first electrode connected to the first conductive type semiconductor layer exposed through at least one contact hole, a second electrode connected to the second conductive type semiconductor layer, a first insulating layer configured to extend from under the light emitting structure to a space between a side of the light emitting structure and the first electrode and configured to reflect light, and a reflective layer disposed under the first insulating layer.

Abstract: Apparatuses, systems, and methods for detecting changes to an IC are disclosed. In an example implementation, an apparatus includes an electromagnetic (EM) sensor. A high-resolution analog-to-digital converter (ADC) is configured to quantize a segment of the EM signal of an IC measured by the EM sensor. The quantized segment of the EM signal is unique to process-voltage-temperature (PVT) characteristics exhibited by the IC. The apparatus also includes a processing circuit configured to prompt the high-resolution ADC, via a control signal, to produce the quantized segment of the EM signal. The processing circuit determines a first signature from the quantized segment and retrieves a baseline signature corresponding to the IC from a data storage circuit. In response to the first signature being different from the baseline signature, the processing circuit indicates that a change to the IC is detected.

Abstract: The present technology relates to a solid-state imaging device and an electronic apparatus that perform a stable overflow from a photodiode and prevent Qs from decreasing and color mixing from occurring. A solid-state imaging device according to an aspect of the present technology includes, at a light receiving surface side of a semiconductor substrate, a charge retention part that generates and retains a charge in response to incident light, an OFD into which the charge saturated at the charge retention part is discharged, and a potential barrier that becomes a barrier of the charge that flows from the charge retention part to the OFD, the OFD including a low concentration OFD and a high concentration OFD having different impurity concentrations of the same type, and the high concentration OFD and the potential barrier being formed at a distance. For example, the present technology is applicable to a CMOS image sensor.

Abstract: A method of fabricating a semiconductor device includes forming first cell patterns on a substrate, forming a first layer relative to the first cell patterns, and forming a second cell pattern and a peripheral pattern on the first layer. The second cell pattern includes first holes in a cell region and the peripheral pattern is located in a peripheral region. The method also includes filling the first holes, removing the second cell pattern to expose pillars, and forming second holes. Each of the second holes corresponds to adjacent cell spacers of the pillars. The method also includes removing the pillars to form third holes corresponding to respective ones of the cell spacers, and etching the substrate using the cell spacers, the first cell patterns, and the peripheral pattern as etch masks to form a trench.

Abstract: A sensor chip includes a first substrate with a first surface and a second surface including at least one CMOS circuit, a first MEMS substrate with a first surface and a second surface on opposing sides of the first MEMS substrate, a second substrate, a second MEMS substrate, and a third substrate including at least one CMOS circuit. The first surface of the first substrate is attached to a packaging substrate and the second surface of the first substrate is attached to the first surface of the first MEMS substrate. The second surface of the first MEMS substrate is attached to the second substrate. The first substrate, the first MEMS substrate, the second substrate and the packaging substrate are provided with electrical inter-connects.

Abstract: Provided is a method of manufacturing a bonded body having a structure where a substrate and an electronic part are bonded to each other with a metal particle paste interposed therebetween. The method includes an assembled body forming step where the electronic part is mounted on the substrate with the metal particle paste interposed therebetween, an assembled body arranging step of arranging the assembled body between two heating plates opposite to one another, and a bonding step of bonding the substrate and the electronic part to each other by heating while applying pressure to the assembled body by moving at least one of two heating plates to the other of two heating plates. The bonding step is performed under a condition that a temperature of the assembled body is within 0° C. to 150° C. In the bonding step, a metal particle paste minimally generates a sintering reaction.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.