Abstract: A shared counter resource, such as a register, is disclosed in the hardware, where the register representing how much free space there is in the command queue is accessible to one or more processing elements. When a processing element reads the “reservation” register, the hardware automatically decrements the available free space by a preconfigured amount (e.g., 1) and returns the value of the free space immediately prior to the read/reservation. If the read returns 0 (or a number less than the preconfigured amount), there was insufficient free space to satisfy the request. In the event there was insufficient space to satisfy the request the reservation register may be configured to reserve however much space was available or to not reserve any space at all. Any number of processing elements may read these registers and various scenarios are described where the input and output queues are accessible via various processing elements.

Abstract: In one embodiment, a method includes: receiving, by a first computer system, a data stream transmitted from a second computer system over a network connection between the first computer system and the second computer system, wherein the data stream comprises executable code of a software program; extracting, by the first computer system, the executable code of the software program from the data stream; allocating, by the first computer system, an amount of dynamic memory for the executable code of the software program; loading, by the first computer system, the executable code of the software program directly into the allocated dynamic memory; and executing, by the first computer system, the software program by launching the executable code of the software program loaded in the allocated dynamic memory.

Abstract: Preamble release training in a double data-rate dynamic random access memory interface uses feedback from read operations to adjust the preamble release signal so that the preamble release signal continues to be activated close to the middle of the preamble. A first signal, and then a second signal, are generated in response to an initiation of a read operation. The first and second signals are characterized by a delay from the initiation of the read operation of one or more clock cycles plus a fine delay contributed by an adjustable delay circuit. The first signal is provided to a data strobe parking circuit that uses it to release or un-park the data strobe signal lines. The second signal is phase-compared with the data strobe signal associated with incoming data during the read operation. The adjustable delay circuit is adjusted in response to the result of the comparison.

Abstract: A graphic processing unit having multiple computational elements flexibly interconnected to memory elements provides for data compressors/decompressors in the memory channels communicating between the computational elements and memory elements to provide an effective increase in bandwidth of those connections by the compression of data transferred thereon.

Abstract: An information processing apparatus included in a parallel computer system has a memory that holds data and a processor including a cache memory that holds a part of the data held on the memory and a processor core that performs arithmetic operations using the data held on the memory or the cache memory. Moreover, the information processing apparatus has a communication device that determines whether data received from a different information processing apparatus is data that the processor core waits for. When the communication device determines that the received data is data that the processor core waits for, the communication device stores the received data on the cache memory. When the communication device determines that the received data is data that the processor core does not wait for, the communication device stores the received data on the memory.

Abstract: System and method for performing program-related operations over a network via a web browser. A network connection is established between a server computer and a client computer over a network. A universal resource identifier (URI) is sent from the client computer to the server computer over the network, where the URI indicates a program, e.g., a graphical program (GP), or at least a portion of a graphical program interactive development environment (GPIDE), e.g., a graphical program editor, an execution engine, a static or dynamic analyzer, and/or compiler. The at least a portion of the GPIDE is received from the server computer over the network in response to the URI, and executed in a web browser of the client computer to perform some specified functionality with respect to the GP.

Abstract: A memory control apparatus includes a temperature obtaining unit, a priority determination unit, and a write processing unit. The temperature obtaining unit is configured to obtain, in a memory having a plurality of measurement areas each including a plurality of unit areas, temperatures measured in the plurality of measurement areas. The priority determination unit is configured to determine a priority for each unit area in accordance with a degree of consumption and the temperature of the measurement area including the unit areas, the degree of consumption being a degree of consumption of the unit area which is caused by a write process performed. The write processing unit is configured to preferentially perform the write process with respect to the unit area having a higher priority as a data write destination.

Abstract: A signal processing device includes an operation control unit configured to control a timing of an operation process executed by an operation unit; and a transfer control unit configured to control a timing of transferring data that is a target of the operation process, such that the data that is the target of the operation process is loaded by the operation unit according to the timing of the operation process controlled by the operation control unit.

Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.

Abstract: Systems and methods for managing storage device commands are provided. A first storage device command is received. A first priority associated with the first storage device command is identified. A plurality of storage device commands that was received before the first storage device command is identified. Each of the plurality of storage device commands is stored in a buffer and organized in a sequence. A determination is made as to whether the first priority associated with the first storage device command is greater than a second priority associated with a second storage device command of the plurality of storage device commands. The first storage device command is added to the buffer at a first position in the sequence that is earlier than a second position of the second storage device command in response to determining the first priority is greater than the second priority.

Abstract: Modular automation system and method are disclosed. A central automation device can be constructed and upgraded using one of a plurality of selectable and variously upgradable baseboards. The automation device can be upgraded using one of a plurality of central units which have uniform external dimensions yet differing data processing power and data storage capacities. At least one input/output expansion device can be directly coupled onto the central unit. Each of the selectable baseboards has a field bus connection interface for a standard field bus connection to a decentral input/output unit.

Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

Abstract: While software in a relay device is being rewritten by an external diagnosis device, a processing unit of the relay device prohibits transfer processing of data from each ECU connected to CAN bus and allows transfer processing of data, which is transmitted from the external diagnosis device and which indicates at least either one of transmission prohibition of periodic transmission data and storage prohibition of a failure code into each ECU by not receiving the periodic transmission data in each ECU, to the CAN buses.

Abstract: Some embodiments provide a system that executes a native code module. During operation, the system obtains the native code module. Next, the system loads the native code module into a secure runtime environment. Finally, the system safely executes the native code module in the secure runtime environment by using a set of software fault isolation (SFI) mechanisms that use predicated store instructions and predicated control flow instructions, wherein each predicated instruction from the predicated store instructions and the predicated control flow instructions is executed if a mask condition associated with the predicated instruction is met.

Abstract: Data is transferred between a requesting application and a storage device by passing the application IO buffer to the disk driver. Techniques are provided to avoid data copying to an intermediate sector aligned buffer and passing the intermediate buffer to the disk driver. The techniques allow the use of layered block device drivers such as a Logical Volume Manager (LVM), Distributed Replicated Block Device (DRBD), or both. A look-ahead can determine the IO constraints imposed by the layered block device drivers. Based on the constraints, an entire portion of the buffer may be added to an IO request, or the buffer may be split into a first portion and a second portion. The first portion may be added to a first IO request. The second portion may be added to a second IO request, different from the first IO request.

Abstract: Methods and systems for a device are provided. The device includes physical function (PF) representing a physical component and is assigned to an XF group. The XF group includes a plurality of virtual functions (VFs) associated with the PF, each VF identified by a unique number. A number of XF group that are assigned to the PF is configurable depending on the function of the physical component.

Abstract: Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.

Abstract: A computer-implemented data processing method comprises receiving information from a user computer concerning a desired output to be generated, adding the information concerning the desired output to be generated to a data structure, and adding additional information to the data structure concerning intermediate outputs to be generated. The information concerning the desired output to be generated is received at a host computer. The host computer is one of a plurality of host computers configured to collect and analyze data received from a plurality of source computers. The data structure represents a list of outputs to be generated by the plurality of host computers. The intermediate outputs are precursor inputs needed to generate the desired output. The additional information is added to the data structure based on the information received from the user computer and based on stored information.

Abstract: The present disclosure includes a method for migration of a first virtual function of a first device located on a PCI bus and accessible by a device driver using a virtual address. A second virtual function is created on a second device. A base address is determined for the second virtual function as a function of a logical location of the second device within the PCI structure. An offset is determined for the second virtual function as a function of the base address and the virtual address. The device driver is notified that the first virtual function is on hold. The offset is stored in a translation table. The device driver is notified that the hold has been lifted. Accesses to the virtual address and by the device driver to memory of the second virtual function are routed based upon the offset in the translation table.

Abstract: Embodiments of the claimed subject matter are directed to methods and a system that allows an application comprising a single code set under the COBOL Programming Language to execute in multiple platforms on the same multi-platform system (such as a mainframe). In one embodiment, a single code set is pre-compiled to determine specific portions of the code set compatible with the host (or prospective) platform. Once the code set has been pre-compiled to determine compatible portions, those portions may be compiled and executed in the host platform. According to these embodiments, an application may be executed from a single code set that is compatible with multiple platforms, thereby potentially reducing the complexity of developing the application for multiple platforms.