Abstract: An apparatus includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a bus that includes a plurality of parallel data lines. The processor is configured to request the memory devices to provide respective status reports, and to receive the status reports from the memory devices such that, in a given clock cycle of the bus, the multiple status reports from the respective memory devices are received in parallel over respective different subsets of the data lines of the bus.

Abstract: Mechanisms provide hosts such as servers and mobile devices with access to virtualized I/O resources including virtual Host Bus Adapters (vHBAs) and virtual Network Interface Cards (vNICs) over a wireless I/O interconnect. Host applications access virtualized I/O resources using virtual device drivers that communicate with virtualized I/O resources on an I/O director using a reliable communication protocol running over a wireless network. I/O data is throttled if necessary based on wireless network considerations.

Abstract: A method comprises measuring the execution time T1 for a problem to be solved with a program being run by a single processor, measuring the execution time TM and TS of MIMD and SIMD program fragments being run by a single processor and a single accelerator correspondingly, determining the specific acceleration ? of the execution time for an SIMD program fragment being run by a single accelerator in comparison with the execution time for the fragment being run by a single processor, determining a portion of the execution time for an MIMD fragment being run by a single processor and a portion of the execution time for an SIMD fragment being run by a single processor and adjusting the quantity of processors or accelerators comprised in a hybrid computing system structure according to the data obtained.

Abstract: Examples are disclosed for establishing a secure destination address range responsive to initiation of a direct memory access (DMA) operation. The examples also include allowing decrypted content obtained as encrypted content from a source memory to be placed at a destination memory based on whether destination memory addresses for the destination memory fall within the secure destination address range.

Abstract: In order to provide a communication apparatus that can reduce the delay in transmission of communication messages even when the bus load is heavy, a data transmission module is connected to a communication bus, over which communication messages are transferred, in such a manner that the data transmission module can transmit/receive the communication messages to/from the communication bus. A bus monitoring unit included in the data transmission module detects, for a given time period, the timings at which communication messages are flowing over the communication bus, and acquires the detection results as usage status data of said time period.

Abstract: When writing code, data structures that include inferred symbols are created based on usage of undefined symbols. As the user continues writing code, code model can be updated to represent updated information based on a learning model. Data structures including inferred symbols can be used by software development tools to provide developer help for symbols that are not yet created or are not yet bound. Inferred symbols can be visually distinguishable making the appearance of the inferred symbol information differ from actual symbol information. The appearance of information based on inferred symbols can be included within tools by activating a particular mode in a programming environment. Conversion of the inferred symbol to a real symbol may trigger the automatic compiler-generation of additional source code by a background compiler. Inferred symbols may be converted to actual symbols by activation of an option to make an inferred symbol a real symbol.

Abstract: A mechanism for executing speculative predicated instructions may include execution of initiating execution of a vector instruction when one or more operands upon which the vector instruction depends are available for use, even if a predicate vector that the vector instruction also depends is not available. If the predicate vector was not available, the results of the execution of the vector instruction may be temporarily held until the predicate vector becomes available, at which time, a destination vector may be updated with the results.

Abstract: Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation.

Abstract: A data processing unit combines a scalar processor and a heterogeneous processor which includes a vector processing array. The vector processing array includes a plurality of vector processors which are operable in a single instruction multiple data configuration.

Abstract: A method and system for operating an application with multiple modes are described. A plurality of applications may be presented to a user on a mobile device and one of the displayed applications may be selected. The selected application may have one or more contexts that are determined based on one or more operational parameters. For example, a context for the selected application may be that the application is configured to access an enterprise account. Based on the context, the selected application may be run on the mobile device in one of a plurality of operations modes. The operation modes may comprise managed, unmanaged, and partially managed modes, among others.

Abstract: A method for verification of a vector execution unit design. The method includes issuing an instruction into a first instance and a second instance of a vector execution unit. The method includes issuing a random operand into a first lane of the first instance of the vector execution unit and into a second lane of the second instance of the vector execution unit. The method further includes receiving results from execution of the instruction and the random operand in both the first and the second instance of the vector execution unit and comparing the received results.

Abstract: The present invention relates to a processor which comprises processing elements that execute instructions in parallel and are connected together with point-to-point communication links called data communication links (DCL). The instructions use DCLs to communicate data between them. In order to realize those communications, they specify the DCLs from which they take their operands, and the DCLs to which they write their results. The DCLs allow the instructions to synchronize their executions and to explicitly manage the data they manipulate. Communications are explicit and are used to realize the storage of temporary variables, which is decoupled from the storage of long-living variables.

Abstract: Methods and apparatus to provide command abstraction. In one embodiment, a method includes obtaining information on commands for a plurality of devices including devices of the same type having different command structures, receiving a generic command from a user directed to one of the devices of the same type, determining, using a computer processor, whether the generic command is supported, extracting parameters from the generic command, and generating from the extracted parameters and the generic command a device-specific command for execution by the one of the devices of the same type.

Abstract: A method for verification of a vector execution unit design. The method includes issuing an instruction into a first instance and a second instance of a vector execution unit. The method includes issuing a random operand into a first lane of the first instance of the vector execution unit and into a second lane of the second instance of the vector execution unit. The method further includes receiving results from execution of the instruction and the random operand in both the first and the second instance of the vector execution unit and comparing the received results.

Abstract: A method includes, in a data storage device, determining an estimated compression ratio. The estimated compression ratio is based on hash values of a subset of a data set. The method includes selectively processing the data set based on the estimated compression ratio prior to storage of data associated with the data set in a memory of the data storage device.

Abstract: A system and method of managing requests from peripherals in a computer system are provided. In the system and method, an input/output memory management unit (IOMMU) receives a peripheral page request (PPR) from a peripheral. In response to a determination that a criterion regarding an available capacity of a PPR log is satisfied, a completion message is sent to the peripheral indicating that the PPR is complete and the PPR is discarded without queuing the PPR in the PPR log.

Abstract: Methods and apparatus related to generating random numbers utilizing the entropic nature of NAND flash memory medium are described. In one embodiment, a data pattern is written to a portion of a non-volatile memory device and is subsequently read multiple times. Based on the read operations, at least one bit is marked for random number generation based at least partially on comparison of a number of flips by the at least one bit and a threshold value. Other embodiments are also disclosed and claimed.

Abstract: An apparatus and method for executing an application within a mobile device is provided. The method includes receiving, at a first device, a message from a second device external to the first device, the message including an application identifier; executing, at the first device, at least one application among a plurality of applications based at least in part on the application identifier; and performing, at the first device, a function of the at least one application based at least in part on a command received from the second device.

Abstract: A migration-destination primary storage apparatus (MD-PDKC) comprises a second PVOL and a second journal storage area storing a journal corresponding to write data for the second PVOL, and executes a data copy to the second PVOL from a first PVOL, which is in a migration-source primary storage apparatus (MS-PDKC) and forms a copy pair with an SVOL in a secondary storage apparatus (SDKC). After the data copy has been completed, the MD-PDKC acquires the latest write sequence information from the MS-PDKC, and upon receiving a write request for the second PVOL, writes the write-request write data to the second PVOL, creates a journal by using journal data corresponding to the write data and also by using update information showing write sequence information based on the acquired latest write sequence information, and writes the journal to the second journal storage area.

Abstract: A computing system a storage device and a file system. The storage device includes a storage area having flash memory. The file system is configured to divide the storage area into multiple zones, multiple sections and multiple blocks, and to write a log in each block. The file system includes a block allocation module. The block allocation module is configured to allocate a target block, in which a log is to be written, by a continuous block allocation method according to which a block having a continuous address with a most recently selected block is set as the target block. The block allocation module is further configured to find a free section from the multiple sections when it is not possible to allocate the target block by the continuous block allocation method, and to set a block in the found free section as the target block.