Patents Examined by Su C. Kim
  • Patent number: 11955590
    Abstract: The present disclosure provides a display panel and a method for making the display panel. The method for making the display panel includes: providing a substrate; preparing a driving circuit layer on one side of the substrate; the driving circuit layer includes a binding layer, a display base and an array circuit layer which are stacked, and the binding layer is located between the display base and the substrate. Removing the substrate and the binding layer is exposed; binding the external control unit on the binding layer.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: April 9, 2024
    Assignee: HKC CORPORATION LIMITED
    Inventors: Zeyao Li, Rongrong Li
  • Patent number: 11955582
    Abstract: A light emitting apparatus includes a substrate, a laminated structure provided at the substrate and including a plurality of columnar sections, and an electrode provided on the side opposite the substrate with respect to the laminated structure and injecting current into the laminated structure. The columnar sections each include an n-type first GaN layer, a p-type second GaN layer, and a light emitting layer provided between the first GaN layer and the second GaN layer. The first GaN layers are provided between the light emitting layers and the substrate. The laminated structure includes a p-type first AlGaN layer. The first AlGaN layer includes a first section provided between the second GaN layers of the columnar sections adjacent to each other and a second section provided between the first section and the electrode and between the columnar sections and the electrode.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: April 9, 2024
    Assignees: SEIKO EPSON CORPORATION, SOPHIA SCHOOL CORPORATION
    Inventors: Hiroyuki Shimada, Katsumi Kishino
  • Patent number: 11955583
    Abstract: A micro-light emitting diode (uLED) device comprises: a mesa comprising: a plurality of semiconductor layers including an n-type layer, an active layer, and a p-type layer; a p-contact layer contacting the p-type layer; a cathode contacting the first sidewall of the n-type layer; a first region of dielectric material that insulates the p-contact layer, the active layer, and a first sidewall of the p-type layer from the cathode; an anode contacting the top surface of the p-contact layer; and a second region of dielectric material that insulates the active layer, a second sidewall of the p-type layer, and the second sidewall of the n-type layer from the anode. The top surface of the p-contact layer has a different planar orientation compared to the first and second sidewalls of the n-type layer. Methods of making and using the uLED devices are also provided.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: April 9, 2024
    Assignee: Lumileds LLC
    Inventors: Yeow Meng Teo, Wee-Hong Ng, Pei-Chee Mah, Chee Chung James Wong, Geok Joo Soh
  • Patent number: 11948970
    Abstract: A semiconductor device includes a semiconductor fin, a gate structure, and a dielectric isolation plug. The semiconductor fin extends along a first direction above a substrate and includes a silicon germanium layer and a silicon layer over the silicon germanium layer. The gate structure extends across the semiconductor fin along a second direction perpendicular to the first direction. The dielectric isolation plug extends downwardly from a top surface of the silicon layer into the silicon germanium layer when viewed in a cross section taken along the first direction.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11948973
    Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Huan-Chieh Su, Shi Ning Ju, Kuan-Ting Pan, Chih-Hao Wang
  • Patent number: 11948994
    Abstract: A semiconductor device includes a substrate having first and second active regions, first and second active patterns on the first and second active regions, first and second gate electrodes running across the first and second active patterns, and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode includes a work function metal pattern and an electrode pattern. The second gate electrode includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern. The first work function metal pattern contains the same impurity as that of the high-k dielectric layer. An impurity concentration of the first work function metal pattern of the second gate electrode is greater than that of the work function metal pattern of the first gate electrode.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: April 2, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byounghoon Lee, Jongho Park, Wandon Kim, Sangjin Hyun
  • Patent number: 11949047
    Abstract: Discussed is a display device having a plurality of semiconductor light emitting elements mounted on a substrate, wherein at least one of the semiconductor light emitting elements includes a first electrode and a second electrode spaced apart each other, a first conductivity type semiconductor layer disposed with the first electrode, a second conductivity type semiconductor layer configured to overlap with the first conductivity type semiconductor layer, and disposed with the second electrode, a first passivation layer covering outer surfaces of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and a second passivation layer covering the first passivation layer, wherein at least one portion of the second electrode is overlapped with at least one portion of the first electrode along the thickness direction of the semiconductor light emitting element.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: April 2, 2024
    Assignee: LG ELECTRONICS INC.
    Inventors: Hwanjoon Choi, Yonghan Lee
  • Patent number: 11942571
    Abstract: This specification discloses LEDs in which the light emitting active region of the semiconductor diode structure is located within an optical cavity defined by a nanostructured layer embedded within the semiconductor diode structure on one side of the active region and a reflector located on the opposite side of the active region from the embedded nanostructured layer. The reflector may, for example, be a conventional specular reflector disposed on or adjacent to a surface of the semiconductor diode structure. Alternatively, the reflector may or comprise a nanostructured layer. The reflector may comprise a nanostructured layer and a specular reflector, with the nanostructured layer disposed adjacent to the specular reflector between the specular reflector and the active region.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 26, 2024
    Assignee: Lumileds LLC
    Inventors: Venkata Ananth Tamma, Toni Lopez
  • Patent number: 11930693
    Abstract: A flexible display device, which has a bending area and a non-bending area, includes a display panel, and a window member disposed on the display panel and including a first glass substrate, a second glass substrate disposed opposite to the second glass substrate, and a bonding layer disposed between the first glass substrate and the second glass substrate. The bonding layer includes a first bonding part overlapping the bending area and a second bonding part overlapping the non-bending area and having a modulus greater than a modulus of the first bonding part.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: March 12, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Kim, Junehyoung Park, Jeongwoo Park, Seungho Kim, Hoikwan Lee
  • Patent number: 11923401
    Abstract: Described are arrays of light emitting diode (LED) devices and methods for their manufacture. An LED array comprises a first mesa comprising a top surface, at least a first LED including a first p-type layer, a first n-type layer and a first color active region and a tunnel junction on the first LED, the top surface comprising a second n-type layer on the tunnel junction. The LED array further comprises an adjacent mesa comprising a top surface, the first LED, a second LED including the second n-type layer, a second p-type layer and a second color active region. There is a first trench separating the first mesa and the adjacent mesa, n-type metallization in the first trench and in electrical contact with the first color active region and the second color active region of the adjacent mesa, and p-type metallization contacts on the n-type layer of the first mesa and on the p-type layer of the adjacent mesa.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: March 5, 2024
    Assignee: Lumileds LLC
    Inventors: Robert Armitage, Isaac Wildeson
  • Patent number: 11923398
    Abstract: An LED array comprises a first mesa comprising a top surface, at least a first LED including a first p-type layer, a first n-type layer and a first color active region and a tunnel junction on the first LED, a second n-type layer on the tunnel junction. The LED array further comprises an adjacent mesa comprising a top surface, the first LED, a second LED including the second n-type layer, a second p-type layer and a second color active region. A first trench separates the first mesa and the adjacent mesa, cathode metallization in the first trench and in electrical contact with the first and the second color active regions of the adjacent mesa, and anode metallization contacts on the n-type layer of the first mesa and on the anode layer of the adjacent mesa. The devices and methods for their manufacture include a thin film transistor (TFT).
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: March 5, 2024
    Assignee: Lumileds LLC
    Inventors: Robert Armitage, Isaac Wildeson
  • Patent number: 11916166
    Abstract: An optoelectronic device may include an optoelectronic semiconductor chip that is configured to emit electromagnetic radiation. The chip may include a first semiconductor layer, a second semiconductor layer, first and second current spreading structures, and a plurality of electrical contact elements. The first current spreading layer may be arranged on a side of the second semiconductor layer facing away from the first semiconductor layer. The plurality of electrical contact elements may electrically connect the first semiconductor layer to the first current spreading layer. The second current spreading layer may be electrically connected to the second semiconductor layer. The second current spreading layer may be arranged between the first current spreading layer and the second semiconductor layer where an insulating layer insulates a first electrical contact element and a second electrical contact element from the second current spreading layer.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: February 27, 2024
    Assignee: Osram OLED GmbH
    Inventors: Roland Heinrich Enzmann, Christian Mueller, Stefan Barthel, Vanessa Eichinger, Marc Christian Nenstiel, Lorenzo Zini
  • Patent number: 11901490
    Abstract: A protection layer for use in fabrication of failure analysis (FA) sample is disclosed, which principally comprises a first thin film, a buffer thin film and a second thin film By forming the protection layer on a surface of a malfunction device die, a FA sample of the malfunction device die is obtained. As a result, in the case of treating the sample with a FIB thinning process, there are no cracks, distortion, and/or collapse resulted from inter-elemental isobaric interferences, stress effect or charge accumulation occurring on the surface layer of the malfunction device die because of the protection of the protection layer. On the other hand, this protection layer can also be applied to a microLED element or a VCSEL element, so as to make microLED element and the VCSEL element possess excellent stress withstanding capability.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: February 13, 2024
    Assignee: YUAN LICENSING CO., LTD.
    Inventors: Chao-Cheng Ting, Hao-Chung Kuo
  • Patent number: 11901397
    Abstract: A light emitting package including a first LED sub-unit, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on the second LED sub-unit, a plurality of connection electrodes electrically connected to at least one of the first, second, and third LED sub-units, the connection electrodes having side surfaces and covering a side surface of at least one of the first, second, and third LED sub-units, a first passivation layer surrounding at least the side surfaces of the connection electrodes, an insulating layer having first and second opposed surfaces, with the first surface facing the LED sub-units, and a first electrode disposed on the first surface of the insulating layer and connected to at least one of the connection electrodes.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: February 13, 2024
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jong Min Jang, Chang Yeon Kim
  • Patent number: 11899365
    Abstract: To provide a photosensitive siloxane composition capable of forming a pattern having a desired taper angle and a desired linewidth. [Means] The present invention provides a photosensitive siloxane composition comprising: a polysiloxane having a structure represented by the following formula (ia?): (L is an alkylene or phenylene), a photoactive agent, and a solvent.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 13, 2024
    Assignee: Merck Patent GmbH
    Inventors: Naofumi Yoshida, Takashi Fuke, Megumi Takahashi, Katsuto Taniguchi, Toshiaki Nonaka
  • Patent number: 11894504
    Abstract: A display apparatus is provided. The display apparatus can include a substrate hole penetrating a device substrate, light-emitting devices spaced away from the substrate hole, and at least one separating device between the substrate hole and the light-emitting devices. Each of the light-emitting devices can include a light-emitting layer between a first electrode and a second electrode. The separating device can surround the substrate hole. The separating device can include at least one under-cut structure. The under-cut structure can include a depth and a length, which are larger than a thickness of the light-emitting layer. Thus, in the display apparatus, the damage of the light-emitting devices due to external moisture permeating through the substrate hole can be prevented.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: February 6, 2024
    Assignee: LG DISPLAY CO., LTD.
    Inventors: So-Young Noh, So-Yeon Je, Ki-Tae Kim, Kyeong-Ju Moon, Hyuk Ji
  • Patent number: 11876156
    Abstract: A light emitting device including first, second, and third light emitting parts disposed near each other and each including a first-type semiconductor layer, a first active layer, and a second-type semiconductor layer, a first pad electrically coupled with the second-type semiconductor layer of the first light emitting part, a second pad electrically coupled with the second-type semiconductor layer of the second light emitting part, a third pad electrically coupled with the second-type semiconductor layer of the third light emitting part, and a common pad electrically coupled with the first-type semiconductor layer of the first, second, and third light emitting parts, in which, in a current density per light emitting part of about 20 A/cm2, one of the first, second, and third light emitting parts that is configured to emit light having the longest peak wavelength has a largest normalized external quantum efficiency.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: January 16, 2024
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Seong Gyu Jang, Ho Joon Lee, Jong Hyeon Chae
  • Patent number: 11855121
    Abstract: A light emitting chip including a first LED sub-unit, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on the second LED sub-unit, a first bonding layer interposed between the first and second LED sub-units, a second bonding layer interposed between second and third LED sub-units, and a first connection electrode electrically connected to and overlapping at least one of the first, second, and third LED sub-units, the first connection electrode having first and second opposing side surfaces, the first side surface having a first length and the second side surface having a second length, in which the difference in length between the first side surface and the second side surface of the first connection electrode is greater than a thickness of at least one of the LED sub-units.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: December 26, 2023
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Min Jang, Chang Yeon Kim, Myoung Hak Yang
  • Patent number: 11843024
    Abstract: A micro LED display device includes a micro light emitting unit, a conductive structure and a substrate. The micro light emitting unit includes a plurality of micro light emitting elements, and each of the micro light emitting elements includes a semiconductor structure and an electrode structure. The semiconductor structure includes a first type semiconductor layer, a light emitting layer and a second type semiconductor layer. The electrode structure includes a first type electrode and a second type electrode. The conductive structure includes a first type conductive layer and a second type conductive layer. The first type conductive layer is electrically connected to the first type electrode, and the second type conductive layer is electrically connected to the second type electrode. The micro light emitting unit is disposed on the substrate, and the electrode structure is disposed toward the substrate and includes a gap therebetween.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: December 12, 2023
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Yu-Yun Lo, Bo-Wei Wu, Yi-Chun Shih, Tzu-Yu Ting, Kuan-Yung Liao
  • Patent number: 11837592
    Abstract: A device includes a substrate having a first surface and a second surface opposite to the first surface; a thin-film transistor array disposed on the first surface, including a plurality of transistors; a plurality of diodes disposed on the thin-film transistor array; a plurality of conductive structures penetrating through the substrate from the first surface to the second surface, wherein the plurality of conductive structures are corresponding to the plurality of diodes and electrically connected to the plurality of diodes; a driver unit disposed on the second surface of the substrate; a patterned conductive layer disposed between the substrate and the driver unit; a protection layer disposed on the patterned conductive layer, wherein the protection layer has an opening that exposes the patterned conductive layer; and a conductive material disposed in the opening.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: December 5, 2023
    Assignee: INNOLUX CORPORATION
    Inventors: Wei-Cheng Chu, Ming-Fu Jiang, Chia-Cheng Liu, Chih-Yuan Lee