Abstract: A method for predicting a failure rate of a semiconductor integrated circuit includes receiving a circuit netlist corresponding to circuit defining data, which defines a connection relation, input, output, size, type and operating temperature of each transistor of a plurality of transistors included in the semiconductor integrated circuit. Low-risk transistors having a low-failure probability among the plurality of transistors are detected and filtered out based on the circuit netlist. Failure rates are calculated of respective high-risk transistors other than the low-risk transistors among the plurality of transistors. A total failure rate of the semiconductor integrated circuit is calculated based on the failure rates of the respective high-risk transistors.

Abstract: A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the retiming of registers in the system driven by a different clock.

Abstract: A method for providing a logic synthesis of a pipeline circuit is disclosed. The method includes: providing a circuit design of the pipeline circuit, wherein the circuit design includes a first logic module as a current stage, and based on an operation of the first logic module, generating a first time marked graph (TMG) that corresponds to a plurality of behavioral phases of the first logic module, wherein the first TMG includes a plurality of vertexes and a plurality of edges, wherein each vertex corresponds to one of the plurality of behavioral phases that occur in sequence and each edge is coupled between two respective vertexes thereby corresponding to a transition from one behavioral phase to another subsequently occurring behavioral phase.

Abstract: A method to easily determine parameters of a second process for manufacturing from parameters of a first process is provided. Metrics representative of differences between the first process and the second process are computed from a number of values of the parameters, which can be measured for the first process and the second process on a calibration layout, or which can be determined from pre-existing values for layouts or reference data for the first process and the second process by an interpolation/extrapolation procedure. A set of metrics are selected so that their combination gives a precise representation of the differences between the first process and the second process in all areas of a target design. Advantageously, the metrics are calculated as a product of convolution of the target design and a compound of a kernel function and a deformation function.

Abstract: A method and apparatus for controlling an on-board charger (OBC) are provided. The method includes monitoring a voltage of an input power source, increasing or decreasing the voltage of the input power source to a preset output voltage of a power factor corrector (PFC), and operating a converter receiving the preset output voltage to adjust a switching frequency of the converter based on a ripple current of an output terminal of the converter. Additionally, the converter includes a first switch configured to receive a first voltage of a first capacitor mounted within the PFC and a second switch configured to receive a second voltage of a second capacitor mounted within the PFC.

Abstract: Disclosed are systems for wireless energy transfer including transcutaneous energy transfer. Embodiments are disclosed for user interface (UI) hubs to connect multiple batteries and to output system information to a patient. Embodiments are further disclosed for garments and devices to be worn by a patient requiring treatment. The garments are configured for a desired placement of a transmitter coil relative to a body of the patient and for facilitating patient comfort and quality of life. Methods for manufacturing and using the devices and the systems are also disclosed.

Abstract: A method comprises forming a grid provided with a plurality of macro nodes. The grid comprises a plurality of meandering electrically conductive circuit paths through the plurality of macro nodes. The method comprises identifying a candidate macro node in the grid which includes only parallel micro node segments and selecting the candidate macro node. The method includes re-arranging the parallel micro node segments of the plurality of micro node meandering electrically conductive circuit paths in the candidate macro node of the grid such that at least one micro node segment is changed electrically to a non-parallel micro node segment in relation to other micro node segments in the candidate macro node to generate data representative of re-arranged meandering electrically conductive circuit paths for the grid. The method includes forming the re-arranged meandering electrically conductive circuit paths for the grid. A computing device and a computer program product for performing the method are also provided.

Abstract: At least one method, apparatus and system disclosed involves providing a functional cell for a circuit layout for an integrated circuit device. A determination as to a first location for a two-dimensional portion of a first power rail in a functional cell is made. A first portion of the first power rail is formed in a first direction. A second portion of the first power rail is formed in a second direction in the first location for the two-dimensional portion.

Abstract: Embodiments disclosed herein provide techniques for representing a routing strip in an integrated circuit design using a digit pattern. According to certain aspects, the techniques include methods to display overlapped routing strips of an integrated circuit design when there are ten or more metal layers in the integrated circuit design. According to additional or alternative aspects, the techniques include methods to generate a texture pattern for displaying routing strips in which layer identification and layer direction of each routing strip can be easily discerned. According to further additional or alternative aspects, the techniques include methods to cause texture patterns for displaying routing strips to stagger with respect to each other when the routing strips are overlapped in a display.

Abstract: The present invention relates to a near-field wireless power transfer system capable of having a constant efficiency regardless of a charging position of a receiver by only using a simple impedance matching circuit without using a separate existing complex adaptive impedance matching circuit or a control circuit, and simultaneously transmitting power without having difficulty with impedance matching even for wireless power transmission to a plurality of electronic devices by applying a structure having a uniform mutual inductance between a wireless power transmitter and a wireless power receiver.

Abstract: A method for designing a system to be implemented on a target device, the method including generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing a corresponding net in the bounding box. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

Abstract: Methods and systems for defect prediction are provided. The method includes receiving feature data of an integrated circuit (IC) and process condition data of a production process associated with the IC, and determining a care area associated with the IC using the feature data, the process condition data, and a defect prediction technique, wherein the care area includes a potential defect and is inspected by a high-resolution inspection system. Based on the provided methods and systems, care areas can be generated incorporating actual process conditions when the inspected IC is being manufactured, and fast and high-resolution IC defect inspection systems can be implemented.

Abstract: A vehicle having a traction battery with at least one cell includes a controller coupled to the traction battery and programmed to control charging and discharging of the traction battery in response to detecting lithium plating in the at least one cell indicated by a ratio of differential voltage of the at least one cell as a function of time to cell charging rate of the at least one cell. In various embodiments, the ratio is compared to a threshold associated with current battery state of charge to indicate lithium plating when the ratio is below the threshold. Lithium plating can also be detected based on a measured cell open circuit voltage (OCV) relative to a previously stored OCV value. In various embodiments, the measured OCV value is calculated based on a measured cell voltage and current, and a previously stored cell internal resistance.

Abstract: A method for converting a real number modeling to a synthesizable register-transfer level emulation in digital mixed signal environments is provided. The method includes verifying an input in a file including a real number modeling code and cleaning the real number modeling code in the file. The method also includes separating a clean register-transfer level code from the real number modeling code, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. The method further includes converting the cycle-driven simulation interface file into a register-transfer level file suitable to perform a circuit emulation in digital mixed signal environments, and verifying that the register-transfer level file is ready to perform circuit emulation in the digital mixed signal environments. A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.

Abstract: A charging device for charging one or more electronic devices is provided. The charging device includes a charging unit configured to include a first charging unit, and a second charging unit, the second charging unit protruding upward from a surface of the charging unit at an angle greater than or equal to a predetermined reference angle with respect to the surface of the charging unit, wherein, if at least one of the first charging unit and the second charging unit is arranged to face at least one electronic device in a face-to-face manner, the at least one of the first charging unit and the second charging unit supplies a wireless power to the at least one electronic device.

Abstract: A wireless power receiver and a method for controlling the wireless power receiver are provided. The wireless power receiver includes a resonant circuit configured to receiving electromagnetic waves from a wireless power transmitter and output alternate current (AC) power, a rectifier configured to rectify the AC power received from the resonant circuit into direct current (DC) power, a DC/DC converter configured to convert the DC power received from the rectifier and output the converted DC power, a battery, a charger configured to charge the battery with the converted DC power, and a controller configured to, upon detection of an event indicating a change in impedance at an output end of the DC/DC converter, control the impedance at the output end of the DC/DC converter and keep the impedance constant by adjusting voltage at the output end of the DC/DC converter.

Abstract: A method and system for detecting defects of integrated circuits have been provided. The method comprises generating process sensitive patterns of an integrated circuit, scanning the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determining care areas of the integrated circuit using the process condition parameters, and scanning the care areas using the high-resolution system to detect at least one defect of the integrated circuit. The system comprises a processor and a memory with instructions executable by the processor to generate process sensitive patterns of an integrated circuit, scan the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determine care areas of the integrated circuit using the process condition parameters, and scan the care areas using the high-resolution system to detect at least one defect of the integrated circuit.

Abstract: Processing a circuit design that specifies application logic and debugging logic includes partitioning the circuit design. Each partition includes a part of the application logic and a part of the debugging logic, each partition is specified for implementation on a respective IC die, and the circuit design specifies connections between a part of the application logic in one partition and a part of the debugging logic in another partition. The connections between the part of the application logic in the one partition and the part of the debugging logic in the other partition are changed to connections from the part of the application logic in the one partition to a part of the debugging logic in the one partition. The part of the application logic and the part of the debugging logic of each partition are placed and routed on the respective IC die.

Abstract: A battery protection circuit includes a voltage source, a first resistor, a charging controller, a first charging transistor, a second resistor, and a current voltage converter. The first resistor includes a first terminal connected to the voltage source. The charging controller supplies a charging control current through a charging control terminal. The first charging transistor includes a gate terminal and a first terminal. The second resistor is connected between the gate terminal and first terminal of the first charging transistor. The current voltage converter is connected to a second terminal of the first resistor to electrically connect the voltage source to the gate terminal of the first charging transistor depending on the charging control current.

Abstract: A method, system, and non-transitory computer readable medium for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern include inserting an internal dummy between a first portion of the guiding pattern and a second portion of the guiding pattern if a vertical spacing is equal to or greater than a first predetermined distance, inserting a first external dummy along an external edge of the guiding pattern in a vertical direction if the vertical spacing is greater than a second predetermined distance, and inserting an anti-taper structure on the first external dummy if a second distance from the external edge of the guiding pattern to an edge of the first external dummy is greater than a first distance.