Abstract: A trigger circuit with switching hysteresis includes first, second and third current sources. A first transistor pair is supplied by the first current source and has transistors with coupled emitters, load circuits and input circuits. The input circuit of one of the transistors of the first pair is acted upon by a reference potential and the input circuit of the other of the transistors of the first pair being acted upon by an input signal. Load resistors are each connected in the load circuit of a respective one of the transistors of the first pair. A coupling resistor interconnects the load circuits of the transistors of the first pair. A second transistor pair is supplied by the second current source and has transistors with coupled emitters, load circuits directly coupled with corresponding load circuits of the transistors of the first pair and input circuits cross-coupled with corresponding load circuits of the transistors of the first pair.

Abstract: The gene encoding the TcpA pilus has been cloned. It encodes a protein useful in live, killed-cell, and synthetic vaccines. Protein production is enhanced by specific medium conditions.

Abstract: The subject invention pertains to the use of recombinant PF4 (rPF4) as well as full length novel analogs (mutants) of rPF4, and peptide fragments thereof, to inhibit angiogenesis. rPF4, analogs, and certain fragments are shown to have utility for treating angiogenic diseases and for the inhibition of endothelial cell proliferation.

Abstract: A driver circuit for driving from the same output node (6) an inductive relay (34) and a non-inductive lamp (30) having a transistor (16) for driving the relay and second transistor (18) for driving the lamp and a third transistor (90) having its current electrodes coupled between the control electrodes of the first and second transistors for sensing an inductively-induced voltage at the output node when the first transistor means is disabled to cease driving the relay and for enabling the first transistor in response thereto to dissipate the inductively-induced voltage at the output node so as to protect the second transistor. Alternative couplings of the third transistor to the second transistor are also disclosed.

Abstract: An amplifier arrangement comprising a first (T1) and a second (T2) field-effect transistor of the same conductivity type and a driver circuit (Q1, Q2, Q3, T3, T4, T5, I) which is responsive to a signal to be amplified at the input terminals (3, 4) to drive the respective drain electrodes of the two field-effect transistors (T1, T2). A resistive element (R) is formed between the drain and the gate electrode of the first field-effect transistor (T1) and a capacitive element (C) is formed between the gate and the source electrode. Together with said elements (R, C) the first field-effect transistor (T1) constitutes a reactance circuit having an inductive character, which is arranged in parallel with the parasitic gate-source capacitance of the second field-effect transistor (T2). This results in an improved step-function response and edge steepness of step-function signals on the output terminal (5), i.e.

Abstract: An avalanche photodiode non-linearity correction circuit cancels a portion of a non-linear recovery error response by the APD to an input signal by using the fact that the non-linear recovery error is only mildly dependent upon the APD gain. The gain of the APD is varied from data acquisition cycle to data acquisition cycle, with the acquired data being stored. The stored data from consecutive data acquisition cycles are combined in a summation circuit to effectively cancel a significant portion of the non-linear recovery error response.

Abstract: A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to a combination of an FM modulator and FM demodulator to provide a delay circuit for an analog circuit.

Abstract: Monoclonal antibodies that recognize a stage-specific antigen on immature human marrow cells are provided. These antibodies are useful in methods of isolating cell suspensions from human blood and marrow that can be employed in bone marrow transplantation. Cell suspensions containing human pluripotent lympho-hematopoietic stem cells are also provided, as well as therapeutic methods employing the cell suspensions.

Abstract: A clock stability circuit (10, 20, 30, 40) assures stable clock generator operation after oscillator start-up, such as during re-entry after a low-power Halt mode in a microprocessor or microcomputer. The clock stability circuit detects stable clock cycles that transition between a selected high amplitude threshold (near VDD) and a selected low amplitude threshold (near VSS), and provides a clock stable signal after a selected number of stable clock cycles, indicating that the oscillator has stabilized. The clock stability circuit includes four modules: input sampler (10), pulse generator (20), pulse counter (30) and control logic (40). The input sampler module includes CMOS NAND gates (11, 14) respectively fabricated with p/n-channel ratios to provide a CLOCK A signal that transitions at the selected high amplitude threshold of an oscillator cycle, and a CLOCK B signal that transitions at the selected low amplitude threshold.

Abstract: An input selection circuit using a plurality of bidirectional analogue switches disclosed which is constituted such that a feedback circuit is installed between the input terminals of a bidirectional analogue switch device and the output terminal of an amplifier, characterized in that the directional conduction deviations of bidirectional switches provided in the bidirectional switch device can be reduced during the transmission of signals. Therefore, the input selection circuit according to the present invention can reduce the signal distortions due to the directional conduction deviations.

Abstract: In the conventional analog switch circuit, an integrating circuit is connected to each gate terminal of a number of analog switches to reduce the switching speed and thus to reduce switching noise. Therefore, when the analog switch circuit is formed into a single IC chip, an area where resistances and capacitances are to be formed is relatively large. To overcome this problem, only two integrating circuits are provided and two integrated switching signals are selectively applied to gate terminals of the analog switches via switches under control of a control circuit, thus realizing an ICed analog switch circuit, while reducing differences in time constant among the analog switches and thus switching noise.

Abstract: This invention accomplishes low power consumption by a drive circuit for a Bloch line memory, which includes a power source, a bias magnetic field coil, a plurality of switching means and means for returning the power supplied to the bias magnetic field to the power source. The present invention can set the waveform of a pulse current (coil current) to a desired waveform by particularly using a transformer, and can improve the transfer characteristics of the Both line pair.

Abstract: A circuit arrangement for transmitting in an undisturbed manner a binary signal through two parallel branches even in case of breakdown, failure or interruption of operating voltages of individual components of a branch, and also to enable a disturbance-free exchanging of individual modules in a branch in which each branch has its own supply means fed by an input for the binary signal to be transmitted, which supply means has two gates together producing an inverting and a non-inverting output. Each branch has its own receiver which is connected to the non-inverted output of the supply means of that branch and the inverting output of the supply means of the other branch. Each receiver includes a difference amplifier which provides the output of the branch, and a network of resistors and diodes which feeds the difference amplifier.

Abstract: A triangle wave generator (10) which is programmable, and which provides variable amplitude, frequency independent, triangle waves over a wide frequency bandwidth while employing a low voltage power source. The triangle wave generator (10) comprises a square wave input signal source (12) and a reference voltage signal source (14). A first amplifier (16) amplifies the square wave input signals and couples them by way of a transformer (34) to an integrator (36,40) which generates triangle wave output signals in response thereto. A second amplifier (18) connected to the triangle wave signal and to the transformer coupled square wave current source for the purpose of providing a bootstrap. A third amplifier (20) samples and compares the triangle wave output signals to the reference voltage signals and generates output error signals in response thereto.

Abstract: The invention comprises antigenic glycoproteins substantially similar to antigenic glycoproteins present on the surface of the merozoite form of Plasmodium falciparum, including glycoproteins of molecular weights of about 56,000 present in the Geneva and FVO isolates and about 50,000 that is present in the Honduras I/CDC, Indochina 1, Kenya and Tanzania I isolates. The invention also comprises monoclonal antibodies 4-8-5D (HB 8938) which bind to the 56,000 glycoprotein of the invention, a hybridoma cell line that is capable of producing these monoclonal antibodies, and vaccines and vaccine compositions comprising these glycoproteins or epitopes substantially similar to or cross reactive with these glycoproteins or genes or gene fragments encoding such epitopes.

Abstract: The power supply circuit supplies electric current to a plurality of circuits in turn. The power supply circuit has a power source (5); a resistor (4); one end of which is connected to the power source (5); a first current path (1), one end of which is connected to the other end of the resistor (4), and including a first driver circuit (12); a second current path (2), one end of which is connected to the other end of the resistor (4), and including a second driver circuit (22); and a controller (3) which drives the first and second driver circuits (12, 22) alternatively. The controller (3) controls the on-and-off timings of the first and second driver circuits (12, 22) so that the first current path (12) is maintained in the ON state for a time equal to or more than a predetermined necessary time, and the second current path (22) is broken for a time equal to or less than an allowed time.

Abstract: A delay circuit for integrated circuits includes a current mirror circuit having at least a pair of MIS transistors, a constant current source and a capacitance. The delay time is determined by the charging time of the capacitance connected to one of the MIS transistors. A stable delay time is obtained regardless of manufacturing variations and the space required for the circuit is reduced.

Abstract: A single 3-terminal integrated circuit for controlling a switching device provides both control terminal voltage limitation and rapid turn off time. In an alternative embodiment the control circuit is contained in the same package which houses the controlled switching device.

Abstract: A semiconductor circuit is provided which has a buffer function, and in which impedance of an output terminal can be set to a high value for a power supply. In another aspect, a semiconductor circuit is provided having an input switching function and in which the scale of the circuit is not excessively large. In both aspects, electric power consumption is small.

Abstract: A MOS (preferably CMOS type) analog NOR amplifier suitable for use in building a programmable array logic (PAL) or the like, or for other usages. The analog NOR amplifier consists of a reference MOS transistor and first pull-up means at one branch and a plurality of input MOS transistors and second pull-up means at another branch with a constant current source connected to the source terminals of these MOS transistors, which forms a configuration similar to a differential amplifier. With the gate terminals of the plurality of input MOS transistors as logic input ends, the drain terminals of the same will act as the output end of a standard NOR gate and the drain terminal of the reference MOS transistor will behave as the output end of a standard OR gate.