Abstract: A Schmitt trigger circuit of the present invention comprises maximum voltage detecting means for detecting and retaining a maximum voltage of an input signal, minimum voltage detecting means for detecting and retaining a minimum voltage of the input signal, and threshold voltage generating means for receiving the detected maximum and minimum voltages and generating threshold voltages.

Abstract: Hybridoma cell lines and transformed B-cell lines are derived from B-cells of cancer patients actively immunized with autologous tumor antigens and used to produce monoclonal antibodies having specificity for tumor-associated antigens. The monoclonal antibodies can be used in both diagnostic procedures and therapy for human cancers.

Abstract: There is provided an improved output circuit having high speed operation and low power dissipation. The circuit having MOS pull up and pull down transistors, wherein a control signal to the pull down MOS is delayed to discharge parasitic capacitance and to prevent both MOS transistors from being on simultaneously.

Abstract: A pulse forming system for providing constant power pulses for variably resistive loads is disclosed. It includes a high voltage power source, a pulse forming network, and a transformer circuit. The high voltage power source outputs a voltage signal with a level of about 200 kV. The pulse forming network receives the voltage signal and outputs a droop compensated rectangular pulse with a selected pulse width, a selected PFN frequency at a first voltage level and a first current value. The transformer receives and transforms the output of the pulse forming network into a selected voltage level and a selected current value for the load while retaining the selected pulse width and PFN frequency.

Abstract: A complementary composite PNP transistor includes a p-channel JFET and an operational amplifier coupled to form an ideal PNP transistor. The positive input of the operational amplifier forms the base of the composite transistor and the drain of the JFET forms the collector of the composite transistor. The anode of a diode-connected NPN transistor forms the emitter of the composite transistor, while the cathode is coupled to the source of the JFET. The diode-connected transistor provides complementary current-voltage characteristics for the composite PNP transistor since the saturation current and g.sub.m of the composite transistor are equal to that of an NPN transistor.

Abstract: A retriggerable multivibrator is disclosed which comprises a first delay circuit connected for delaying an input signal a predetermined time, a second delay circuit connected to receive an output of the first delay circuit and having a enable or disable function, a flip-flop circuit connected to be set or reset in accordance with an input signal and output signal from the second delay circuit, and a control circuit for detecting a subsequent input signal within a predetermined delay time to enable or disable the second delay circuit.

Abstract: A peak detector circuit utilizes a comparator to compare an input signal to a peak voltage output signal. The output of the comparator enables a charging current source to charge a holding capacitor at a first rate when the input signal is greater than the peak voltage output signal and enables a discharging current source to discharge the holding capacitor at a second rate when the input signal is less than the peak voltage output signal. The capacitor voltage is coupled through the gate to source of an n-channel transistor and this source voltage forms the peak voltage output signal.

Abstract: A circuit arrangement reduces the time necessary for a voltage-to-frequency converter to provide a new output frequency in response to a change in input voltage levels. A current source provides additional input current to the input integrating node of the v/f before a conversion is requested. When a conversion is requested, the additional input current effectively provides operation of the v/f at an increased frequency, thus speeding the settling process therefor. When the integrator of the v/f is at a predetermined voltage level in a predetermined operating cycle, the current source is removed, thus terminating the increased frequency of operation.

Abstract: An output buffer circuit comprises a NAND circuit and a NOR circuit each receiving an output a of a signal source and an output b of an output control circuit and an output driving circuit formed by a p channel MOS transistor and an n channel MOS transistor receiving outputs of the NAND circuit and the NOR circuit. Large output capacitance is connected to an output of the output driving circuit. The n channel MOS transistor is connected between the output of the NOR circuit and a ground potential, and has its gate receiving the output of the output driving circuit. When the output of the output driving circuit is at an "H" level, the rise of the output of the NOR circuit is controlled, so that the output of the output driving circuit is first changed to the "L" level slowly. Therefore, discharge current from the output capacitance rises slowly.

Abstract: Respective current supply means (I.sub.A, I.sub.B) control conducting periods of corresponding transistors (Q.sub.3, Q.sub.4), whereby conducting periods of driving transistore (Q.sub.6, Q.sub.7) are also controlled. Thus, periods in which both of the driving transistors (Q.sub.6, Q.sub.7) simultaneously enter ON states are reduced and through current (I.sub.S) flowing to the ground level GND through the driving transistors (Q.sub.6, Q.sub.7) is reduced. A pull-down transistor (Q.sub.8) controls a conducting period of the driving transistor (Q.sub.7), whereby periods in which both of the driving transistors (Q.sub.6, Q.sub.7) simultaneously enter ON states are reduced and the through current (I.sub.S) is reduced.

Abstract: A sense amplifier 10 for a memory or logic array has a bipolar device transistor 11 that is kept from saturating by one or more unipolar transistors (12, 13) coupled between the collector (18) and base (17) of the bipolar transistor 11.

Abstract: A low driving voltage operation logic circuit responsive to a power source voltage applied between a pair of power source terminals for modifying an input signal according to a predetermined logic pattern. The logic circuit includes an input control circuit having a plurality of input transistors for generating a pair of control signals, each having a level opposite to the other, in response to the input signal and a differential circuit having a plurality of paired transistors for dividing the frequency of the control signals, the input transistors each having an emitter area substantially larger than the emitter area of each paired transistor and the logic circuit including only a single base to emitter junction corresponding to each input transistor between the power source terminals.

Abstract: A protection device for suppressing higher frequency interference pulses in an input signal for an electric circuit includes a transistor whose emitter is grounded via a current source to act as an emitter follower for an input signal. The voltage drop of the base-emitter diode of the transistor is compensated for by a corresponding voltage drop across a diode whose anode is connected to a voltage supply line via a second current source. A junction point of the second current source and the diode is connected to a capacitor which together with the second current source forms a low-pass member for the input signal. A Schmitt-trigger circuit is connected to the junction point to restore lower frequency input pulses from trapezoidal pulses picked up at the capacitor.

Abstract: An output driver for high performance integrated circuits. The driver dynamically compensates for variations in temperature, voltage and process. To perform the compensation, the driver is divided into two parts: static and transient. The static part is used to maintain the DC level. The transient part is active only during logic 0 to 1 and 1 to 0 transitions and is used only to assist the static part during such transitions. A closed loop feedback technique is used to compensate the driver for temperature, process, and voltage variations; specifically, a scaled down version of an output driver is used to monitor speed variations due to temperature, process, and voltage, the output of which is fed back to the output driver which then performs the necessary compensation.

Abstract: A current divider circuit includes a node (22) which receives a signal current (I) and divides the signal current (I) between one or more first current paths formed by a first type of impedance element (T1' to TN') and one or more second current paths (28) formed by a type or types of impedance element (21, 22) dissimilar to the first type. Each second current path terminates in an output branch of a current mirror circuit (32). The input branch of each such current mirror circuit is connected to the node (22) via a further current path (30) formed by the first type of impedance element (T0'). The provision of the further current path(s) (30) and current mirror circuit(s) (32) ensures that a predetermined proportion of the total signal current can be made to flow into each current path, even though the second current path(s) (28) may contain arbitrary or unknown impedances. The circuit can also be used to control the voltage at the node (22) as well as dividing the received signal current.

Abstract: A novel sense amplifier is taught which minimizes power consumption by causing selected current sources to conduct current only when an input signal of a selected state is present. The speed of the circuit is fast because capacitance on the critical nodes is minimized by connection of fewer transistors to the critical nodes, as compared with the prior art.

Abstract: An integrated circuit comprising logic circuits and at least one push-pull stage. In order to reduce the magnitude of induction voltages on power supply lines of the circuit, caused by the current variations in the push-pull stage comprising a push transistor and a pull transistor, a first current through one transistor is kept substantially constant until after a most significant rise of a second current through the other transistor when the push-pull stage is switched. A push-pull stage produces lower induction voltages during switching can thus be realized without adversely affecting the switching speed.

Abstract: An integrated circuit is disclosed with a logic network having an output coupled to a sense node and having a virtual ground node, and with a sense amplifier having a sensing circuit coupled to the sense node to provide an output signal, charging and discharging feedback circuits coupled to the sense node that limit the swing of the sense amplifier, and an enable control to enable and disable the sense amplifer. In one embodiment in a CMOS integrated circuit a parallel network of n-channel transistors has an output connected to a sense node of a sense amplifier. A sensing inverter and a feedback inverter are connected to this sense node. The switchpoint of the feedback inverter is substantially higher than the switchpoint of the sensing inverter. A charging n-channel transistor is connected between the sense node and a power supply for charging the sense node, and the output of the feedback inverter is connected to the gate of the charging transistor.

Abstract: The reference voltage generating circuit in this invention for generating a constant reference voltage in a semiconductor device, is provided with a low voltage applying line for applying to the circuit a voltage less than a supply voltage, standby current controlling means connected to said low voltage applying line for reducing greatly the standby current flowing in the circuit, a resistance component connected to said standby current controlling means for forming said reference voltage, a reference voltage output line connected to a connection node between said standby current controlling means and said resistance component, and initial voltage forming means connected in parallel with said standby current controlling means between said low voltage applying line and said reference voltage output line.

Abstract: A combinational static CMOS logic circuit for providing a plurality of basic two-input logic functions with reduced complexity and integrated circuit area. The combinational static CMOS logic circuit provides either a NAND or an XOR output at a first output terminal and a NOR output at a second output terminal. A configuration input terminal is utilized for selecting between the NAND or the XOR output being provided at the first output terminal. In an alternate configuration, the combinational static CMOS logic circuit provides either a NOR or an XNOR output at a first output terminal and a NAND output at a second output terminal.