Abstract: An electrically programmable non-volatile memory comprises word lines (LM2) extending along rows, and bit lines (LB1) extending along columns. Each memory point (PM1) is constituted by a pair of MOS transistors (T22, T23) having a floating gate (23). A conductive area (25) is connected to the floating gates (23) of the two transistors (T22, T23) of each pair and is in register with the word line (LM2) connected to the memory point (PM1) made by the transistor pair. This word line (LM2) corresponds, at the position of this pair, to the control gate (28).

Abstract: In the semiconductor memory device according to the present invention, a n type drain diffused region (9a) to be connected to a bit line (12) is formed on a p type semiconductor substrate (1) and a n type source diffused region (9b) is formed with a prescribed spacing from the n type drain region (9a). On the p type silicon substrate (1), a p type diffused region (16a) of high impurity density and p type diffused region (16b) of high impurity density are formed in such a manner that they are in contact with the n type drain diffused region (9a) and the n type source diffused region (9b), respectively, but not in the channel region of the n channel MOS transistor (18). Consequently, the .alpha. particle-generated charges can be decreased without changing the threshold voltage of the transfer gate transistor.

Abstract: A semiconductor integrated circuit device having a wiring line of aluminum film or aluminum alloy film covered with a silicon insulation film and connected to the semiconductor region formed on the principal surface of a single crystal silicon substrate, with a polycrystalline silicon film interposed, wherein said silicon film is a polycrystalline silicon film composed of large crystal grains which is formed by depositing in amorphous state and then heat-treating the deposited film, said polycrystalline silicon film reduces the amount of silicon atoms which separates out in said wiring line. Also said wiring line is provided with a shielding film which is disposed between said insulation film and at least the upper surface and lower surface of said wiring line and which prevents silicon atoms from separating out from said insulation film.

Abstract: The described embodiments of the present invention provide DRAM cells, structures and manufacturing methods. A DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit.

Abstract: In a semiconductor fabrication technique, a first patterned layer (16) of nonmonocrystalline semiconductor material is created on a substructure (10, 12, 14). An insulating layer (22) is thermally grown along the patterned layer in such a way that the upper edge of the remainder (16A) of the patterned layer forms an asperity (24). A blanket layer 26, preferably consisting of nonmonocrystalline semiconductor material, is formed over the insulating layer. Using an etchant that attacks the blanket and patterned layers more than the insulating layer, a selective etch is performed to remove a section of the blanket layer. The etch is continued past the blanket layer to remove the underlying portion of the insulating layer located along the asperity and then, importantly, to remove the so exposed part of the asperity. The remainder (26A) of the blanket overlies the remainder ( (24A) of the asperity.

Abstract: A capacitor is formed for use with a DRAM storage cell by lying down alternating layers of polycrystalline silicon for the storage node and the ground plate. A buried bit line allows the capacitor area to cover a significant fraction of the cell layout area. The alternating storage node and ground plates of the capacitor are laid down alternately, and connected together as they are formed. The number of interleaved layers which can be used to form the capacitor can easily be varied to suit process requirements.

Abstract: A method of making bipolar and MOS devices simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution.

Abstract: Island layers defined by grooves are formed on a p.sup.+ -type silicon substrate. One memory cell having a MOS capacitor and a MOSFET transistor is formed in each island layer. The MOS capacitor is buried in a groove surrounding the island layer and has a capacitor electrode insulatively provided over the bottom surface of the groove and an n.sup.- -type semiconductor layer formed in a ring-shaped manner in the side surface region of the groove and facing the capacitor electrode. The MOSFET has a ring-shaped gate electrode for in the groove to be insulatively stacked over the capacitor electrode. The gate electrode faces a p-type channel region formed in a ring-shaped manner in the side surface region of the island layer. Only a drain layer is formed in the top surface region of the island layer.

Abstract: Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned polysilicon p-channel pull-up transistors without appreciably enlarging the cell area.

Abstract: A field effect transistor includes a high concentration doping layer self-alignedly produced using a refractory metal silicide gate as a mask for ion implantation in a semi-insulating substrate. The distance between the refractory metal gate and the high concentration doping layer which becomes a source region is shorter than the distance between the refractory metal gate and a high concentration doping layer which becomes a drain region.A method of producing a field effect transistor having an offset refractory metal silicide gate includes depositing a refractory metal silicide layer, a refractory metal film, and a first insulator film successively on an active layer which is produced on a semi-insulating substate. The deposited layers are patterned with a resist film for producing a gate pattern mask for etching the respective layers all at once or one-by-one. High dopant concentration source and drain regions are formed by ion implantation and annealing.

Abstract: An array of floating gate memory cells is formed at a face of a semiconductor layer (10). The array includes a plurality of elongate spaced-apart parallel source/drain regions (12). A thick dielectric layer (14) is formed on the face. A plurality of spaced-apart orifices (16) are formed through the thick dielectric layer (14) to the face, each orifice exposing portions of two adjacent source/drain regions (12) and extending therebetween. A plurality of thin first gate insulators (18) are formed on the face in the orifices (16). Next, conductive floating gate electrodes (20) are formed on the orifices (16) and the first gate insulators (18), with the combined thickness of a floating gate electrode (20) and a first gate insulator (18) approximating the thickness of the thick dielectric layer (14). A planarized surface is thus presented for the deposition of an interlevel insulator (22, 24) and a plurality of control gate electrodes (26).

Abstract: In order to reduce alignment errors arising in the fabrication of semiconductor integrated circuits using electron beam lithography, enhanced registration marks--(i.e., registration marks that are more easily and accurately detectable by the electron beam)--are formed at the edges of oxide layers, located at the surface of a silicon body, by means of forming metal silicide layers having edges coincident with the edges of the oxide layers. Advantageously, the enhancing of the registgration marks by forming the metal silicide is performed subsequent to any high temperature processing steps, whereby the integrity of the marks is maintained.

Abstract: For making an inter-level insulating film between a capacitor electrode and a gate electrode mild at the shoulder portion thereof, a doped polysilicon film is overlain by a silicon oxide film on a dielectric film structure, and the silicon oxide film is slightly etched through an isotropical technique by using a mask layer for forming a hollow space with a generally quarter-circle configuration beneath the mask layer, then anisotropically etching the silicon oxide and the doped polysilicon by using the same mask layer, then depositing silicon oxide on the entire surface, then exposing the surface of a semiconductor substrate by using an etch-back technique for leaving the inter-level insulating film on the capacitor electrode, then forming a gate electrode on the inter-level insulating film.

Abstract: The specification discloses an isolation trench (36) formed in a semiconductor body. A stress relief layer (38) of oxide is formed on the interior walls of the trench (36), the layer (38) being sufficiently thin to prevent stressing of the lower corners of the trench (36). A masking layer (40) of nitride is formed over the layer (38). An isolation body (42) of oxide or polysilicon then refills the remainder of the trench and a cap oxide (43) and layer (44) of field oxide is formed over the semiconductor body and the filled trench.

Abstract: A dynamic semiconductor memory device comprising a substrate having one trench including two capacitors for memory cell capacitances of two bits, and two elements such as transistors for reading, writing, and storing information represented by charge, arranged symmetrically at the central portion of the trench so as to correspond to the memory cells for two bits, and a field oxide film formed at the center of the trench on the bottom and on the side walls for separating the capacitors and elements.

Abstract: A semiconductor device of the complementary metal-insulator semiconductor type is composed of a pair of N-type metal oxide semiconductor transistor formed on a P-type silicon substrate and P-type metal oxide semiconductor transistor formed on an n-type well disposed within the p-type substrate. An isolation tranch is disposed between the pair of adjacent transistors, and has one sidewall bordering the well, another opposed sidewall bordering the substrate, and a bottom wall. A selective epitaxial film of p-type is selectively epitaxially deposited on the sidewalls and bottom wall of the trench. The epitaxial film has a dopant density greater than that of the substrate. An insulation oxide material is filled within the trench so as to effectively isolate the pair of transistors from each other.

Abstract: An electrically erasable, programmable read only memory (EEPROM) having an erase window directly overlying both a control gate layer (24) and a column line (12) is disclosed. Column lines (12) are implanted into a semiconductor substrate (16) and covered with a first insulating layer (18). A floating gate layer (20) overlies the first insulating layer (18) and is covered with a second insulating layer (22). The control gate layer (24) overlies the control insulating layer (22) and is covered by a third insulating layer (26). A passage (28) extends through the third insulating layer (26), control gate layer (24) and second insulating layer (22) and contains a sidewall insulator (30) on walls thereof. A tunnel oxide (32) resides within the passage (28) and is contacted by a programming electrode layer (34) which additionally overlies the third insulating layer (26) and fills the passage (28).

Abstract: The present invention provides a semiconductor memory device comprising a MOSFET (16) and a storage capacity element (15) and performing data writing/reading.The MOSFET (16) is formed on a main surface of a silicon substrate (1) and a storage capacity element (15) is formed on a surface of the reverse side of the silicon substrate (1). The MOSFET (16) comprises source and drain regions (3, 4) formed on the main surface of the silicon substrate (1), a channel region (17) positioned therebetween and a word line forming a gate electrode (9a).

Abstract: The described embodiments of the present invention provide DRAM cells, structures and manufaturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit.

Abstract: A method for fabricating a semiconductor memory device which includes a single substrate, at least one memory cell including at least one MOS transistor formed on the single substrate, and a peripheral circuit having at least one MOS transistor formed on the single substrate, comprises the steps of forming on the single substrate a gate electrode for each of the MOS transistors of the memory cell and the peripheral circuit, iono-implanting impurities at a low dosage by using the gate electrodes as a mask so as to forming a low impurity concentration of source/drain regions of the MOS transistors of the memory cell and the peripheral circuit, depositing a mask layer to cover an area of the memory cell, and ion-implanting impurities at a high dosage by using the mask layer as a mask, so as to dope impurities to only the source/drain regions of the MOS transistor of the peripheral circuit, so that the MOS transistor of the memory cell has the source/drain regions of a low impurity concentration, and the MOS tran