Abstract: A chip having field effect transistors which have differing threshold voltages determined in a single masking step and a method of making the chip provides a chip usable at both cryogenic and room temperatures without a costly additionaly masking step. The chip has devices with low threshold voltages that are therefore optimized for performance at low temperatures, and devices with high threshold voltages that are optimized for performance at higher temperatures. Such high threshold voltage devices are also usable, though sub-optimally, at lower temeperatures such as cryogenic temperatures. The two sets of devices have their threshold voltages determined in a single masking step, with the higher threshold voltage values being provided during this step by reducing the width of a device to produce a parasitic effect.

Abstract: A field effect transistor is made with a source and drain which are utilized partly as a semiconductor region in a semiconductor body, and partly as a portion of a deposited epitaxial layer. A recess is formed into a substrate of the semiconductor body between the source and drain, and a channel region underlies the recess in the substrate. As a result of this construction, the channel length is independent of variations in the thickness of the epitaxial layer, and the stray capacitances from source and drain to the substrate are small. Moreover, a conductor pattern, separated from the epitaxial layer by an insulating layer, may extend to be on the connection zones of the source and drain, which involves a high packing density. The epitaxial layer, moreover, comprises extra wiring tracks. This gives a greater freedom in design.

Abstract: A CMOS silicon-on-insulation structure is fabricated by first forming an insulating SiO.sub.2 layer on a silicon substrate having a (110) plane. Openings are then formed in the SiO.sub.2 layer to expose a part of the substrate, and a polycrystalline or an amorphous silicon layer is deposited on the SiO.sub.2 layer and in the openings. The deposited silicon layer is divided into islands so that a first island includes one of the openings and a second island does not include any openings. A laser beam is then irradiated onto the islands so as to melt the islands, and when the laser light irradiation is discontinued, the melted islands recrystallize so that the first island forms a (110) plane and the second island forms a (100) plane. A p-channel MOSFET is fabricated on the first island, and an n-channel MOSFET is fabricated on the second island.

Abstract: A method for manufacturing twin well type semi-conductor devices includes the steps of forming a first layer on a P-type silicon substrate, selectively removing part of the first layer to expose a predetermined portion of the surface of the substrate, ion-implanting phosphorus to introduce the phosphorus into the surface area of the substrate under the first layer and into a portion of the substrate deeper than the substrate surface area below the predetermined portion of the substrate surface, ion-implanting boron to introduce the boron into the surface area of the first layer and the surface area under the predetermined portion of the substrate, removing the first layer, and effecting heat treatment to diffuse the introduced phosphorus and boron.

Abstract: A method of manufacturing a semiconductor device with overvoltage self-protection of punchthrough type comprises the following steps.(a) A step of making a recess in a P gate-base layer from its surface exposed to the top surface of a substrate. In this step, the recess is formed to such depth that a space-charge layer produced in the gate-base layer when a predetermined breakover voltage for self-protection is applied to a thyristor reaches at least the bottom of the recess, and the bottom of the recess extends close to a junction between the gate-base layer and an emitter layer.(b) A step of doping the gate-base layer with P type impurities from the bottom of the recess to gate-base layer to form a region of low impurity concentration just under the bottom of the recess. The amount (atoms/cm.sup.2) of the P type impurities is substantially equal to N.sub.D .times.

Abstract: A method of making a self-aligned FET includes the following steps. First, selectively doped heterostructure substrate having a predetermined crystalline structure is obtained having a heavily doped top GaAs layer, having a heavily doped AlGaAs layer under the top layer that is resistant to orientation-dependent etching, and having an undoped underlying AlGaAs layer and an undoped bottom GaAs layer. Then, an uppermost GaAs layer is deposited on the top layer. Then, an angular recess is etched through the uppermost GaAs layer and through the top heavily doped GaAs layer of the heterostructure substrate with an orientation-dependent etchant down to the etch resistant AlGaAs layer, whereby the length of the angular recess is wider at the base of the recess than at the top of the recess because of the predetermined crystalline structure and the orientation-dependent etchant. Next, a refractory metal gate of tantalum silicide is deposited in the recess.

Abstract: A semiconductor device having at least one P-N junction and a multiple-zone junction termination extension (JTE) region which uniformly merges with the reverse blocking junction is disclosed. The blocking junction is graded into multiple zones of lower concentration dopant adjacent termination to facilitate merging of the JTE to the blocking junction and placing of the JTE at or near the high field point of the blocking junction. Preferably, the JTE region substantially overlaps the graded blocking junction region. A novel device fabrication method is also provided which eliminates the prior art step of separately diffusing the JTE region.

Abstract: A complementary MOS one-capacitor dynamic RAM cell which operates with a non-boosted wordline without a threshold loss problem and which includes one storage capacitor and n- and p-type transfer devices connected to the storage capacitor which function as two complementary transistor devices having gates controlled by complementary signals on the RAM wordlines.

Abstract: In a semiconductor memory integrated circuit comprising a semiconductor substrate with a surface trench, a thick oxide film is formed to cover the inner wall of the trench substrate except part thereof where the inner wall is exposed. A cell capacitor comprises a lower electrode, a dielectric layer and an upper electrode, the lower electrode being in contact with the exposed part of the inner wall of the trench. A cell transfer transistor is formed in the semiconductor substrate adjacent to the cell capacitor, wherein one of the diffusion layers is in contact with the lower electrode of the cell capacitor at the exposed part of the inner wall of the trench.

Abstract: A D-RAM is disclosed which isolates the capacitors of memory cells and also isolates the adjacent memory cells by utilizing trenches formed on a semiconductor substrate. The device is particularly intended to the area of each memory cell and prevent the occurrence of a leakage current between the adjacent memory cells. Two side walls of the trench are used as the capacitors of two different memory cells, respectively, and these capacitors are isolated from each other by a thick oxide film that is formed on the bottom of each trench.

Abstract: This invention relates generally to dynamic random access, semiconductor memory arrays and more specifically relates to an ultra dense dynamic random access memory array. It also relates to a method of fabricating such arrays using a plurality of etch and refill steps which includes a differential etching step which is a key step in forming insulating conduits which themselves are adapted to hold a pair of field effect transistor gates of the adjacent transfer devices of one device memory cells. The differential etch step provides spaced apart device regions and an insulation region of reduced height between the trenches which space apart the memory cells. The resulting structure includes a plurality of rows of vertically arranged field effect transistors wherein the substrate effectively acts as a counterelectrode surrounding the insulated drain regions of each of the one device memory cells. A pair of gates are disposed in insulating conduits which run perpendicular to the rows of memory cells.

Abstract: A first semiconductor layer is formed on a semiconductor anode layer containing a high concentration of impurity of a first conductivity type. This first semiconductor layer contains an impurity in a lower concentration than the impurity concentration of the anode layer on which it is formed. A second semiconductor layer containing a high concentration of impurity of a second conductive type is formed on the first semiconductor layer, and a third semiconductor layer containing a low concentration of impurity of the second conductive type is formed on the second semiconductor layer. Impurity regions of at least the first conductivity type are formed by thermal diffusion in the surface region of this third semiconductor layer. During the thermal diffusion, the impurity contained in the anode layer diffuses into the first semiconductor layer.

Abstract: A two-terminal, bidirectional semiconductor trigger switch is provided. The trigger switch is a relatively sensitive multilayer semiconductor breakover device that switches on fully when its breakover voltage is reached. The design of the trigger switch allows its breakover voltage point to be readily adjustable during fabrication of the device.The semiconductor trigger switch is particularly suited to provide a low voltage trigger for a TRIAC. The trigger switch is connected in series with the gate of the TRIAC and mounted on the gate lead to provide a unitary, three-terminal device incorporating the TRIAC/trigger switch combination.

Abstract: An integrated light-triggered and light-quenched static induction thyristor and fabrication process thereof adapted in such a manner that an integrated SIPT operates in the normal mode in order to enhance current gain, tail current generated at the light-quenching time is reduced in order to enhance turn-off gain, and an buried-gate type of light-triggered static induction thyristor and a photo-darlington circuit composed of a first and second static induction phototransistors are integrated on a high-resistivity substrate in order to permit manufacturing said thyristor compact as a whole in facilitated processes.

Abstract: A silicon integrated circuit includes a vertical power DMOS transistor and a vertical NPN transistor in separate epitaxial pockets by a method including simultaneously forming a plurality of D-well regions in the DMOS transistor and the base region in the NPN transistor, and including simultaneously forming the elemental source regions and the emitter region. N-type buried layers are provided simultaneously in the DMOS and the NPN transistors, respectively. Also formed simultaneously are two N+ plugs connecting the two buried layers, respectively, to the epitaxial surface of the integrated circuit die. None of these economically attractive simultaneous steps requires deviation in either device from optimum geometries. Also disclosed are compatible and integrated steps for forming small signal CMOS transistors. This method also includes a full self-alignment of gate, source and channel regions in the DMOS transistor as well as in the CMOS transistors.

Abstract: This invention concerns a method and an apparatus for measuring and testing the electric characteristic of a semiconductor device in a non-contact fashion. For conducting measurement and testing in a non-contact fashion, an electron beam is used to induce a voltage, on a semiconductor device which is an object to be tested (an object to be measured.) By changes with lapse of time of the induced voltage, the electric characteristic, of the semiconductor device are determined. Thus, an electron beam is irradiated to an object to be tested to induce a voltage thereafter to examine changes in the induced voltage. Then, the electric characteristic of the semiconductor device is measured and tested from the voltage thus induced and the voltage measured thereafter.

Abstract: A semiconductor memory comprises a p.sup.- -type semiconductor substrate (1), a p-type epitaxial layer (15) and p.sup.+ -type epitaxial layers (16, 17) formed thereon, an n.sup.+ -type region (6) formed on the p.sup.+ -type epitaxial layer (16) to serve as a bit line, an n.sup.+ -type region (5) formed on the p.sup.+ -type epitaxial layer (17) to serve as a charge storage region and a gate electrode (9) formed on the p-type epitaxial layer (15) to serve as a word line. The p.sup.+ -type epitaxial layers (16, 17) prevent passage of electrons within electron-hole pairs induced by alpha rays, to suppress occurrence of soft errors. The p-type epitaxial layer (15) defines a region corresponding to the channel region of a bus transistor, whereby the impurity concentration thereof can be easily controlled, to readily set the threshold voltage of the bus transistor at an appropriate level.

Abstract: In a semiconductor integrated circuit device, such as a ROM having an instruction program set therein, in which an order for selecting word lines is variously different depending upon written information; a method of manufacture which can shorten a production process after the determination of the instruction program or the circuit arrangement of a decoder without adding to a manufacturing step is disclosed.

Abstract: The disclosed method of forming a capacitor on a semiconductor substrate includes the steps of filling a trench in the semiconductor substrate with a photoresist, a step of exposing the photoresist in situ to a standing wave of light intensity which is created by interference between incident light directed to the bottom of the trench and reflected light from the bottom of the trench, developing and exposed photoresist in situ to leave periodic photoresist regions along the side wall of the trench in the direction of its depth, and etching the side wall using the residual periodic photoresist as a mask to create periodic hollows along the side wall of the trench.

Abstract: A capacitive pressure transducer comprising:field effect solid state electronic device having a semiconductor gate area, an insulating layer and a gate element;the gate element being made of conducting material and being constructed to move in response to pressure differentials on the two sides thereof so as to function as a diaphragm;the gate element being hermetically sealed along its perimeter with the said insulating layer;the gate element also being a conductor so as to change the capacitance between the said gate element and the semiconductor of said field effect solid state device and cause any change in the output of said solid state electronic device to be a measure of the change of the pressure;and a method of making the suspended diaphragm and gate element.