Abstract: A data collection unit obtains physiological data from a subject interface on a subject. The subject interface can be connected to the data collection unit. When the subject interface is connected to the data collection unit, subject interface contacts on the subject interface make contact with data collection unit contacts on the data collection unit. Some of the data collection unit contacts are for communicating physiological data from the subject interface to the data collection unit. Some of the contacts are for powering the data collection unit upon the subject interface being connected to the data collection unit and for powering down the data collection unit upon the subject interface being disconnected from the data collection unit.

Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Abstract: Aspects include computing devices, apparatus, and methods for accelerating distributive virtual memory (DVM) message processing in a computing device. DVM message interceptors may be positioned in various locations within a DVM network of a computing device so that DVM messages may be intercepted before reaching certain DVM destinations. A DVM message interceptor may receive a broadcast DVM message from first DVM source. The DVM message interceptor may determine whether a preemptive DVM message response should be returned to the DVM source on behalf of the DVM destination. When certain criteria are met, the DVM message interceptor may generate a preemptive DVM message response to the broadcast DVM message, and send the preemptive DVM message response to the DVM source.

Abstract: Server computers may include one or more input/output (I/O) adapter devices for communicating with a network and/or direct-attached device. The I/O adapter device may implement processes to manage write requests in a general and flexible manner. The I/O adapter device may also implement processes to manage write requests in a fast an efficient—that is, low latency—manner. Low latency write requests processes may include determining that a write packet for a write request can be processed without additional assistance from a processor, once a processor has initiated a memory access request to fetch write data and also generated protocol information for transmitting the write packet. The I/O adapter device may then process and transmit the write packet through an offload pipeline, without interrupting a processor.

Abstract: A system for communicating information includes one device that communicates information via a communication link. The system also includes a second device to communicate information via the communication link. The second device includes a receiver to receive information from the communication link. The second device also includes an oscillator that provides at least one timing signal to the receiver. The oscillator is disabled when the communication link is in an idle state. The oscillator is enabled when the communication link is in a non-idle state.

Abstract: A communication device includes a communication unit configured to communicate with a LAN, and IO ports connectable to a manufacturing apparatus, and a controller. The IO ports are configured and/or programmed to exchange ON/OFF signals including multiple bits with the manufacturing apparatus. The controller is configured and/or programmed to receive communication requests from communication destinations via the LAN, store network addresses of communication destinations and IO port designations, change a value of the ON/OFF signals of designated IO ports in accordance with requests from communication destinations, and transmit the ON/OFF signals of designated IO ports to communication destinations via the communication unit and the LAN in accordance with requests from the communication destinations.

Abstract: A process control system includes an I/O module configured to be connected to a field device which is installed in a plant in which an industrial process is controlled, the I/O module autonomously transmitting data received from the field device, and a higher-level device that comprises a memory which temporarily stores the data autonomously transmitted from the I/O module, the higher-level device reading the data stored in the memory at a predetermined period.

Abstract: A system for evaluating a stream of sensor data formed by means of at least one sensor for a plurality of value documents includes at least two evaluation units and a data bus. Each of the evaluation units has first and second interfaces for receiving or transferring the sensor data stream with the sensor data, a third interface for receiving and transferring evaluation data, a working memory, at least one processor connected to the working memory for evaluating the sensor data in the working memory, and a relaying device connected to the first and the second interfaces and to the working memory for receiving a sensor data stream received via the first interface, at least partial relaying to the second interface and to storage of at least part of the data of the sensor data stream in the working memory, with the data bus being connected to the third interface.

Abstract: A method of controlling direct memory access of a peripheral memory of a peripheral by a master is described. The method includes checking whether there is a pending request from the peripheral for a direct memory access service, establishing whether an access condition is satisfied in dependence on at least whether there is a pending request, and, if the access condition is satisfied, granting access to the master. Also, an associated device and an associated computer program product are described.

Abstract: A control system includes a switch circuit, a buffering circuit, and a motherboard. The switch circuit is configured to output a switch signal having a trigger time. The buffering circuit determines whether the trigger time of the switch signal is equal to a predetermined time. If the trigger time of the switch signal is equal to the predetermined time, the buffering circuit outputs a signal to the motherboard. The motherboard performs a power off operation.

Abstract: A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.

Abstract: The present invention provides integrated circuit and apparatus having USB connector; the integrated circuit includes a signaling circuit and an interface for relaying signal between the USB connector and the signaling circuit, wherein an interconnect scheme of the signaling circuit is different from USB interconnect defined by USB specification; for example, a frequency adopted for signaling can be programmable, be lower than wireless band and/or be different from a frequency of USB SuperSpeed interconnect.

Abstract: A multi-port transmitter device for transmitting at least partly redundant data is described. The multi-port transmitter device comprises at least two transmitters comprising respective transmitter buffers. One transmitter is a master transmitter that issues a request to the processor to provide a data block when the transmitter buffer of the master transmitter has free space to store a data block. The processor is arranged to copy at least one data block of data stored in an external memory from the external memory to respective positions in a local buffer. The processor is arranged to, in accordance with a predefined sequence, sequentially initiate transfer of the data block from the respective position of the data block in the local buffer to the transmitter buffers of the at least two transmitters in response to a request from the master transmitter to provide a data block.

Abstract: A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus.

Abstract: A method for data communication in a serial LIN bus system that is used to transmit LIN information between a LIN master and LIN slaves includes transmitting the LIN information between the LIN master and the identical LIN slaves via respective data line that run between each of the identical LIN slaves and the LIN master.

Abstract: Systems and methods are described for dynamically detecting outliers in a set of input/output (I/O) metrics collected and aggregated by a storage volume network. An I/O request is received by a storage volume network, and an agent of the storage volume network associates primary and secondary identifiers with that I/O request. For example, a trace may be associated with a request to write data to a storage volume network, and spans may be associated with the individual operations required to fulfill that request. Once gathered, I/O metrics may be aggregated based on the associated identifiers. I/O metric information regarding outliers may be received from the storage volume network, processed, and published by an I/O metrics service to identify the outliers among the primary and secondary identifiers. These outliers may then be stored for further analysis, and may be utilized to determine improvements to the performance of a storage volume network.

Abstract: Embodiments herein provide for efficient memory mapping in a PCIe device when a host changes memory allocations in the device. One PCIe device comprises a plurality of Base Address Registers (BARs) defined by the host. The device also includes a processor with an address space. The processor maps addresses of the address space to the BARs for routing PCIe packets from the host. The processor can determine that the host is reconfiguring the BARs, and, based on the determination, mark packets existing in the computer memory as old, change the BARs in the computer memory as directed by the host, mark packets received after the BAR change as new, process the old packets from the computer memory based on their addresses of the address space until a new packet is reached, and to remap the BARs to the addresses of the address space after the new packet is reached.

Abstract: A method for a card reader to communicate with an upper computer comprises: initializing a card reader system and enabling an interrupt; determining an interrupt identification type; for Bluetooth communication interrupt identification resetting or USB communication interrupt identification resetting, receiving an instruction and saving a channel identification corresponding to the instruction, performing a corresponding operation according to an instruction type, sending a corresponding response to the upper computer and clearing the Bluetooth communication interrupt identification or the USB communication interrupt identification; for another interrupt identification, performing a corresponding operation according to an interrupt identification type. The method can solve a problem in prior art that a card reader cannot communicate with mobile devices of different models through a USB port.

Abstract: A system, method, and computer-readable medium are disclosed for entitling the implementation of a feature associated with a device after it is manufactured. A feature entitlement management system receives a device's unique identifier, which is then processed to determine which features associated with the device are available for implementation. Once determined, the available features are provided to the user of the device, who in turn selects a feature for implementation. A feature entitlement is then generated by performing late binding entitlement operations to associate the selected feature's corresponding entitlement data with the device's unique identifier. The resulting feature entitlement is then is processed to implement the selected feature.

Abstract: A computer system includes a system component with at least one expansion bus and at least one processor coupled to the at least one expansion bus and executes program code of at least one operating system. The computer system also includes a system management module arranged on the system component and at least one memory. The system management module is coupled to the at least one expansion bus and the at least one expansion bus allows direct access to the at least one memory. The system management module has an interface that implements a protocol stack having a bidirectional transport layer used to provide a predetermined shared memory area of the at least one memory to interchange data with the operating system.