Abstract: An eMMC includes flash memory including an extended card specific data (CSD) register (“EXT_CSD register”), and an eMMC controller that controls operation of the flash memory. The eMMC controller is receives a clock from a host via a clock line, receives a SEND_EXT_CSD command from the host via a command line, and provides the host with eMMC information stored in the EXT_CSD register via a data bus in response to the SEND_EXT_CSD command, the eMMC information including maximum operating frequency information for the eMMC.

Abstract: Methods and systems for automatically creating a cluster are provided. The method includes discovering at least a first and a second intelligent storage adapter, determining if the first or the second intelligent storage adapter is operating within a cluster, and when neither the first or the second intelligent storage adapter are a part of any cluster, then automatically generating a cluster with a unique identifier and assigning one of the first or the second intelligent storage adapters as a master of the cluster.

Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.

Abstract: Provided is an apparatus including a first storage device having a first write speed and a second storage device having a second write speed. The apparatus also includes a controller configured to manage a transfer of data to the first storage device or the second storage device. The amount of data stored on each of the first and second storage devices is based on the first write speed and the second write speed.

Abstract: Methods of using a peripheral component interconnect express (PCIe) device in a virtual environment are disclosed. Two operating systems operate on a primary device. One operating system acts as a guest in a virtual environment within the primary device. A peripheral device is coupled to the primary device through a wireless connection. In an exemplary embodiment, the wireless connection is a PCIe bridge. The host operating system interfaces directly with the memory elements and hardware of the primary device. The guest operating system interoperates with the memory elements and hardware of the peripheral device. The use of the PCIe wireless link allows the guest operating system to interface with the elements of the peripheral device with relatively little latency.

Abstract: The invention provides the data flow communication control between the source (flash/IO) and destination (IO/flash) cores. The source and destination cores are started simultaneously instead of serially and get instructions from the descriptors provided and set-up by the processor. Each source and destination core's descriptors1 are correlated or tied with each other by the processor by providing information to the hardware assist mechanism. The hardware assist mechanism responsible for moderating the data transfer from source to destination. The flow tracker guarantees that data needed by destination exists. 1 Descriptors are set of instructions that is used to activate the DMA controller. By applying the invention to the prior approach/solution, the data latency between the flash & IO bus will be reduced. Processor interrupts will be minimized while data transfer between the flash & IO bus is ongoing.

Abstract: In some example embodiments, there may be provided a method, which may include sending, by a user equipment, a first predetermined test pattern to a first accessory including a first connector, when the first accessory is in a first mode of operation; determining, by the user equipment, a configuration of the first accessory in the first mode by at least measuring a first time for the first predetermined test pattern to return from the first connector and a data loop at the first accessory; sending, by the user equipment, a second predetermined test pattern via at least the first connector; and determining, by the user equipment, a presence of a data loop extension, by at least measuring a second time for the second predetermined test pattern to return from the first connector and at least one of the data loop at the first accessory or the data loop extension.

Abstract: A bus node for an electric coupling of a bus system to a functional module arrangement, having an electronic circuit for converting electrical signals between a bus protocol provided by the bus system and an internal communications protocol provided by the functional module arrangement, and having a first coupling means for electrically connecting the electronic circuit to the functional module arrangement, and having a second coupling means for electrically connecting the electronic circuit to the bus system, wherein the first coupling means comprises a first contact means that is configured for a direct electrical contact with a ground connection of the functional module arrangement.

Abstract: One embodiment is directed to a communication media including one or more communication paths extending from a first end to a second end and a first connector assembly terminating the first end of the one or more communication paths. The first connector assembly includes a physical layer management (PLM) interface that is isolated from signals on the one or more communication paths. The first connector assembly also includes a programmable processor coupled to a storage device and coupled to the PLM interface. The programmable processor is configured to perform secure communications with another device coupled to the PLM interface to communicate physical layer information regarding the communication media to the other device. An aggregation point can associate a first port on the other device to which the first connector assembly is inserted with the first connector assembly or the communication media using the physical layer information.

Abstract: Parallel storage system testing is provided. An input/output (I/O) pattern is received. One or more sets of jobs are determined, based, at least in part, on the I/O pattern. Each of the one or more sets of jobs identifies one or more jobs. Each job identifies one or more I/O operations. Each set of jobs of the one or more sets of jobs is assigned to a processing node of one or more processing nodes. The one or more sets of jobs are executed concurrently.

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

Abstract: Present disclosure relates to a computer-implemented method for handling two SES sidebands using one SMBUS controller. The method includes one or more of following operations: (a) establishing communication between a backplane controller and a host computer through HBA, (b) receiving control commands and control data from host computer for monitoring and controlling at least one drive of first and second group of drives, (c) determining address and device number of drive to which received control commands and control data are directed, (d) forwarding control commands and control data to first or second SMBUS sideband handler based on address received, (e) controlling the blinking of the LEDs of the drive by first or second SMBUS sideband handler, (f) generating responses by the first or second SMBUS sideband handler, (g) receiving responses by the SMBUS controller, and (h) sending the responses back to the host computer within a predetermined time period.

Abstract: System and methods are provided for managing universal-serial-bus (USB) data transfers. An example system includes a non-transitory computer-readable storage medium including a first scheduling queue for sorting endpoints and a host controller. The host controller is configured to: store a plurality of endpoints for data transfers to the storage medium, an endpoint corresponding to a portion of a USB device; sort the plurality of endpoints in a first order; generate a first transmission data unit including multiple original data packets, the original data packets being allocated to the plurality of endpoints based at least in part on the first order; and transfer the first transmission data unit.

Abstract: An accessory device architecture is described. In one or more implementations, data is received from an accessory device at an intermediate processor of a computing device, the data usable to enumerate functionality of the accessory device for operation as part of a computing device that includes the intermediate processor. The data is passed by the intermediate processor to an operating system executed on processor of the computing device to enumerate the functionality of the accessory device as part of the intermediate processor.

Abstract: A virtualization based system comprises a host and a plurality of virtual machines that may each comprises a guest memory. A virtual machine monitor has access to underlying platform hardware in the system and may control physical resources in the platform. The platform hardware comprises a processor and a memory coupled to the processor. Further, the VMM may manage guest software including guest operating systems running on the virtual machines. A binary translation logic may replace guest memory writing instructions corresponding to a hot spot in guest application with translated codes to generate a mirrored content for the guest memory. The binary translation logic may combine one or more of the guest memory writing instructions in a region and keep the region atomic. The processor may execute the translated codes in an atomic region together to write a content in the guest memory and a mirrored content in a mirroring memory. The VMM may allocate a memory region in the host memory for the mirroring memory.

Abstract: A message control program of an embodiment causes a monitoring apparatus to further function as a plurality of message control unit configured to individually controlling a communication method of a message transmitted from each internal application unit. Each message control unit receives a message containing a message type and service name from the internal application unit. Each message control unit specifies communication method identification information from a file based on the message type and service name in the received message. Each message control unit changes the communication method of the received message based on the specified communication method identification information, and sends the message to a common bus.

Abstract: An apparatus and method are disclosed in which unrelated completion operations intended for a single destination (requestor) are coalesced to improve achievable data bandwidth. During transmission, the completion operations are collected and compressed into a single packet and transmitted along the link. At a receiving end of the link, the single packet is decompressed and the previously unrelated packets are returned to their initial state before receipt by the requestor. The method can be implemented in the root complex, end points, and/or switches, in the case of a PCIe implementation, but can also be applied to other protocols besides PCIe.

Abstract: The present invention relates to an external device extension method and an external device. The external device is provided with a storage device interface and firmware for implementing operation requests of standard functions of the storage device interface. When the external device is connected to a host, the firmware communicates with the host according to standards of the storage device interface, so that the external device is identified by the host as a standard external storage device, and one or more of operation names, parameter names, data names, and/or device status names supported by the external device are simulated as one or more directories and/or files. Upon receiving a standard directory and/or file read/write request from the host, the external device executes a corresponding external device operation instruction, processes written data, and returns, according to the read request, data formatted according to the request from the host.

Abstract: Embodiments of the present invention provide for a remotely controllable electrical socket. Such sockets may include an electrical conductor for receiving a plug of an electrical device. The plug may be associated with a tag for receiving identifying information that corresponds to the electrical device. Exemplary sockets may further include a tag reader for obtaining identifying information from the tag, a sensor for detecting if the plug is inserted in the outlet, and a communications interface for wirelessly sending information to a computing device regarding the identifying information and whether the plug is inserted in the outlet. The communications interface may also receive operational instructions from the computing device (e.g., to turn the power to the plug/electrical device ON or OFF).

Abstract: An access system includes line cards. The line cards include first and second line cards. The first line card receives a first packet and includes a first interface control module that generates a first request signal to transfer the first packet. The first request signal includes an identifier of a second interface control module in the second line card. Crossbar modules are separate from the line cards and include first and second crossbar modules. The first crossbar module includes a first scheduler module. The second crossbar module transfers packets between a pair of the line cards. The packets include the first packet. The first scheduler module is separate from the line cards and, based on the first request signal, schedules the transfer of the packets from the first interface control module, through the second crossbar module, and to the second interface control module.